Board A — USB-PD Core

The small, cheap, reusable USB-PD 15V sink board (STUSB4500 + USB-C + load switch + NVM/debug pads) — the fixed circuit per the board-split decision (#90).

Board A is the USB-PD front end split out of the single-board zudo-pd design (epic #86). It negotiates a 15 V/3 A USB-PD contract with a STUSB4500, load-switches it, and hands the switched rail to Board B (the synth power stage) over a 6-pin cable connector. This page documents the fixed circuit — the front end after the board-split decision (#90) fix list is applied — not the failed v4 circuit described in v4 USB-PD Failure Diagnosis.

Purpose

• Cheap, re-orderable debug surface. The STUSB4500 front end was the source of two failed JLCPCB orders (v3's pin-18 bug, v4's CC-termination and D4-rating defects — see the diagnosis page). Splitting it onto its own small board means a bring-up failure only costs a re-spin of this board, not the whole multi-stage power supply.

• Reusable USB-PD 15 V sink module. Nothing on Board A or its output connector is synth-specific: it is a generic "negotiate 15 V over USB-PD, switch it, expose GND + two status flags" module, usable in any other project that needs a PD-negotiated DC rail.

• NVM-programmable. The same board carries the I2C pogo pads used to write the STUSB4500's PDO configuration — see NVM Programming Setup.

Block diagram

Net-connectivity table (fixed circuit)

Per Net-Table + Mermaid Convention. Read directly from scripts/schgen/board_a_spec.py's NETS table — the spec module that generates boards/board-a/board-a.kicad_sch — so, unlike the wave-3 version of this page, the #90 fix-list deltas (D4 removed; R17/R18 DNP; R19/R20 rewired; D5-D7 added; J4 added as Board A's new A↔B interface connector) plus the wave-6 D8 gate-clamp addition are written into a real KiCad file; they are just not written back into the legacy usb-pd-input.kicad_sch sheet, which stays the as-built v4 reference (see root CLAUDE.md, "Legacy root KiCad project").

Deltas vs the current single-board circuit

Board A's schematic is usb-pd-input.kicad_sch (the current single-board design) plus exactly these changes — the same list locked in board-split-decision.md §A6, items 1–5 (items 6–8 of that list are linear-regulation.kicad_sch/dc-dc-conversion.kicad_sch edits that belong to Board B, not Board A):

Removed

• D4 (USBLC6-2SC6, C7519) — deleted entirely, not relocated. Its VBUS-clamp role was a hard abs-max violation (6 V-rated zener on a 15 V rail); its CC-ESD role duplicated U1's own integrated 22 V-rated protection while adding a silent-failure class (candidate 3: CC continuity relying on a part-internal flow-through).

Set DNP (footprint kept, not populated, excluded from BOM/CPL)

• R17 / R18 (5.1 kΩ external Rd) — kept as rework insurance only. Fitting them in parallel with U1's own always-on internal 5.1 kΩ Rd puts the CC termination out of the USB Type-C sink window the moment U1 powers up (2.55 kΩ effective) — the v4 blocker.

Rewired

• R19 pin 2: GND → CC1 (restores CC1DB↔CC1 dead-battery termination, ST's reference topology for a VBUS-only sink).

• R20 pin 2: GND → CC2 (restores CC2DB↔CC2).

• CC1/CC2 connector-to-chip path: now direct copper (previously routed through D4's internal pin 1↔6 / 3↔4 flow-through).

Added

• D5 = SMAJ20A (SMA, unidirectional TVS), cathode on VBUS_IN, anode on GND. Clones the existing SMAJ15A_C571368 symbol/footprint pattern (used by TVS1/TVS3 on the linear-regulation sheet) into a new SMAJ20A_C571370 entry.

• D6 / D7 = Nexperia PESD24VS1UB (SOD-523), DNP, one per CC line to GND. Layout provision only — fit for enclosed/production builds, not the bring-up/debug build.

• J4 = the new Board A ↔ Board B interface connector (JST B6B-XH-A, 6-pin) — see below. This did not exist on the single-board design (the front end fed the DC-DC sheet directly through the shared VBUS_OUT net); Board A terminates that net at J4 instead.

• D8 = BZT52C11-7-F (SOD-123-class, LCSC C92321), zener across Q1's gate-source: cathode on VBUS_IN (Q1 source), anode on Net-(Q1-G). Wave-6 addition (decision (e), scripts/schgen/decisions.json) — a fitted hardware guard for the case where an unprogrammed STUSB4500 (factory NVM advertises PDO3 = 20 V/1 A at highest priority) is first plugged into a 20 V-capable charger: without a clamp, the R11/R12 divider drives Q1's Vgs to −12.82 V, 0.82 V past the ±12 V abs-max, with no hardware interlock. The zener's 10.4–11.6 V Vz window sits below its knee at the legal 15 V contract (|Vgs| 9.62 V) and clamps the gate-source voltage in every reachable state, including the −20.77 V transient a D5 clamp event can otherwise reach. R11/R12 values and topology are untouched — this is purely additive. See Programming order and the D8 gate clamp below and NVM Programming Setup for the companion procedural guard.

Unchanged (re-confirmed correct, do not touch)

• Pin-18 network: VBUS_IN → R14 (470 Ω) → U1 pin 18 (the v3 fix).

• Q1 gate network (R11/R12/C35).

• VDD/VREG decoupling (C1/C2/C30/C34/C35).

• I2C NVM programming path (J2, R15/R16).

• Debug pogo block J3.

• Test points TP1/TP2/TP6.

Load switch: Q1 gate network and soft-start

Q1 (AO3401A, UMW LCSC C347476) is the high-side pass element between VBUS_IN and VBUS_OUT. Three parts shape its gate, all sitting on Net-(Q1-G) per scripts/schgen/board_a_spec.py:

Soft-start time constant

τ = R12 × C35 = 56 kΩ × 100 nF = 5.6 ms

C35 slows the gate's fall when U1 asserts VBEN, limiting dV/dt on VBUS_OUT at turn-on and so limiting inrush into Board B's input bulk capacitance (940 µF total after the wave-6 C5/C7 swap — see Board B).

Conduction loss and the package ceiling

At the PD contract's 3.0 A cap the conduction loss P = I² × Rds(on) lands between 0.45 W (3² × 50 mΩ) and 0.59 W (3² × 65 mΩ). The bracket is not a rounding detail: the driven gate sits at 9.62 V, just short of the datasheet's −10 V test point, so the 50 mΩ number is not guaranteed here and the −4.5 V point is the conservative bound. The steady-state package ceiling is (150 °C − 25 °C) / 125 °C/W ≈ 1.0 W at 25 °C ambient, leaving roughly 1.7× margin in the worst case — enough, but thin enough to be worth a thermal check once Board A's copper pour exists.

Why a P-channel high-side switch

P-channel is what lets U1's open-drain VBEN pin drive the gate directly through R12 against the R11 pull-up, with no charge pump anywhere on the board — and it keeps the A↔B ground return unbroken at J4 pins 5–6, which a low-side switch would not.

Power sequencing (VBUS_EN_SNK)

U1 sequences the load switch itself through VBUS_EN_SNK (pin 16, net VBEN — active-low open-drain), so VBUS_OUT only rises after a contract exists. This is what keeps Board B's input bulk capacitance from drawing inrush during negotiation, when the port is still at 5 V and the source is still deciding.

Because Q1 stays off until VBEN asserts, TP1 (VBUS_OUT) reads 0 V during NVM programming — that is correct behavior, not a fault. See the bring-up tip under Test points.

Component list, LCSC parts, and rough cost

All LCSC part numbers below are read from the current schematic's netlist export (source of truth), not from the general BOM page, which has drifted on a few passive LCSC numbers since this front end was last exported. Prices are rough JLCPCB catalog estimates — re-verify at order time.

DNP (footprint only, not populated — no per-board cost):

Rough per-board total (fitted parts only): ~$2.90. U1 alone is ~86% of that — this is an inherent cost of the STUSB4500, not something Board A's split-out changes. What the split does change: this board has roughly a quarter of the single-board design's unique Extended-part count (U1, J1, J4, D5, D8 vs. the full board's ~20), so JLCPCB's per-unique-part setup/Extended fees amortize much faster on a small reorder batch — the actual point of "cheap, re-orderable." Fabrication, stencil, setup, and Extended-part fees are separate from the component total above; see BOM for the general JLCPCB fee structure (those figures describe the full single-board order, not Board A alone).

J1 substitution options

If C456012 is out of stock, these 6-pin power-only USB Type-C receptacles were screened as candidates:

Stock figures are from that screening pass, not current — re-check at order time. Verify the pad map before substituting. Board A's footprint (TYPE-C-SMD_TYPE-C-6P) expects A5 = CC1, B5 = CC2, A9/B9 = VBUS, and A12/B12 plus the four shell tabs (all numbered 7) = GND — see fact-usb-type-c-009-cc-pins and the net table above. Most 6-pin power-only receptacles follow the same GND–VBUS–CC1 / CC2–VBUS–GND arrangement, but it is the pad numbering that has to match, not the physical order. A full 24-pin receptacle carries the same power and CC contacts and would work electrically, but it needs its own footprint; the 6-pin part is chosen for cost on a power-only port.

A↔B interface contract (LOCKED — copied verbatim from #90)

Connector (both boards): JST B6B-XH-A(LF)(SN) — 6-pin top-entry shrouded THT header, 2.5 mm pitch, LCSC C144397 (genuine JST; stock listed 2026-07-05, re-verify at order time). Rated 3 A/contact (AWG #22), 250 V. Cable: commodity pre-crimped 6-way XH↔XH, AWG 22, 80–150 mm (or JST XHP-6 housings + SXH-001T-P0.6 contacts — verify stock at order time; cable-side parts are not on the PCBA BOM).

Current-rating math: worst case = PD contract cap 3.0 A @ 15 V (computed steady draw ≈2.5 A at the rated 26.5 W output budget). XH contact nameplate 3.0 A; 80% continuous derate → 2.4 A/contact. 2 contacts per power rail → 4.8 A derated capacity; at 3.0 A each contact carries 1.5 A = 50% of nameplate → 1.6× derated margin (2.0× nameplate). GND identical (2 contacts, symmetric return). Cable drop ≈16 mV round trip at 3 A (2× AWG 22 per leg, 100 mm) — negligible.

Keying/foolproofing: XH shrouded housing is mechanically polarized (reversed insertion blocked). Uniqueness rule: the 6-pin XH is the ONLY 6-position XH on either board. Pin 1 silkscreened on both boards.

Mechanical (LOCKED): side-by-side, cable-linked. Stacking rejected: USB-C must reach the enclosure wall, Board A's J2 pogo pads need face access for the NVM rig, Board B's TO-263 regulators need top-side copper/airflow, and a stack fixes relative orientation (hurts reuse). Each board carries its own 4× M3 (3.2 mm) mounting holes; no shared hole pattern.

Genericity: nothing synth-specific on the connector — 15 V power, GND, two generic open-drain status lines; a consumer that ignores pins 3–4 just gets switched 15 V.

On Board A, this connector is designated J4 (next free reference after J1 USB-C, J2 NVM pogo, J3 debug pogo) and carries VBUS_OUT (pins 1–2), ATT (pin 3), PDOK (pin 4), and GND (pins 5–6) per the net table above.

NVM programming interface, debug pads, and test points

J2 — NVM programming (pogo, 1×4, 2.54 mm)

Bare-copper pogo pads (no BOM cost), used with a pogo-pin clip and a NUCLEO-F072RB acting as a USB-to-I2C bridge. Full procedure, wiring, GUI steps, and pitfall table in NVM Programming Setup.

Three ways to get a programmed part, in the order this project considered them:

1. NUCLEO-F072RB as a USB-to-I2C bridge, driven by ST's STSW-STUSB002 GUI — the flow actually used here. Wiring, firmware choice (UART, not HID), and the pitfall table are in NVM Programming Setup; the STEVAL-ISC005V1 eval board is not needed, since the STUSB4500 is already soldered to this board.

2. Any MCU over I2C — community flasher code at usb-c/STUSB4500.

3. Distributor pre-programming — some distributors will write the NVM before shipping, which removes the J2 step from assembly entirely. Not used here, because the PDO set was still moving; it is the option that scales once the configuration is locked.

J3 — debug pads (pogo, 1×8, 2.54 mm)

Test points

Programming order and the D8 gate clamp

D8 (see Deltas vs the current single-board circuit above) is a complementary hardware guard, not a substitute for the procedural one: it bounds the specific Q1 Vgs overage a 20 V contract or a D5 clamp event would otherwise cause, but the NVM itself must still be programmed and locked to ≤15 V before the board sees a charger that could offer more.

Bring-up troubleshooting

Symptom-first table for Board A. Reference designators are Board A's, per scripts/schgen/board_a_spec.py; the deeper NVM-side decision tree ("is the chip even alive?") lives in NVM Programming Setup.

Reuse guidance for other projects

Board A is designed to drop into any project that just needs a switched, PD-negotiated DC rail — not only this synth power supply.

Minimum wiring to reuse Board A standalone:

• Connect J4 pins 1–2 (VBUS_OUT) and pins 5–6 (GND) to the consuming circuit. That alone gives a plain switched-15 V sink module.

• Pins 3 (ATT) and 4 (PDOK) may be left unconnected — Board A negotiates and switches power on its own; nothing downstream needs to read these flags. If a consumer wants sequencing/fault info, pull each up externally (10–100 kΩ to a local rail ≤5 V) per the interface contract above.

NVM reconfiguration for other voltages: the negotiated voltage/current live entirely in the STUSB4500's NVM (see NVM Programming Setup), not in the schematic. A reuse project can reprogram J2 for a different PDO instead of 15 V/3 A without a hardware change only up to and including 15 V — this board's locked electrical exposure is bench-verified only at that contract. Reprogramming to 20 V is not currently safe on the as-documented hardware: the wave-5 evidence review found the Q1 gate divider exceeds its Vgs abs-max at a 20 V contract (finding BA-1) and D5's standoff margin drops to zero at exactly 20 V (finding BA-4). The wave-6 D8 gate clamp (above) closes the Q1 exposure, but D5 and the STUSB4500 pin exposures below are not re-evaluated for a 20 V contract. Do not reprogram above 15 V without re-deriving these margins for the target voltage.

Electrical limits to respect:

• VBUS_IN/VDD's operating range tops out at 22 V (DS12499, mirror-sourced); the absolute maximum is a separate, higher figure — 28 V (also mirror-only; the primary ST datasheet DS12499 could not be retrieved to confirm it, so treat this ceiling as evidence-capped, not primary-confirmed). D5 (SMAJ20A) is chosen for its 20 V standoff / 22.2–24.5 V breakdown, but its ≤32.4 V clamp table point sits above every one of these ceilings (32.4 > 28 > 22), not under any of them — the clamp does not protect VDD from a fault event; it only sets the outer bound the STUSB4500's own 28 V mirror-only rating would need to survive. This overage is a recorded, accepted transient-class residual (disposition ba2-disposition, scripts/schgen/decisions.json), not a design guarantee — D5 stays SMAJ20A because no lower-clamping 20 V-standoff part is currently fitted; a lower-clamping SMBJ20A upgrade is recorded as a future Board A layout-phase option.

• Q1 (AO3401A) is rated −30 V/−4 A on VDS — comfortably above the 15 V/3 A design point. Its Vgs rating is the tighter limit and is now bounded by D8 (above), not by margin alone.

• J4's 2 contacts per power rail give a 1.6× derated-current margin at the 3.0 A PD contract cap (see the current-rating math above); do not exceed that per-board 3 A cap when reusing Board A at higher currents without re-deriving the connector margin.

• A downstream circuit connected to VBUS_OUT must tolerate the ≤32.4 V transient clamp ceiling of D5 during a fault event, not just the nominal 15 V.

Mechanical: Board A carries its own 4× M3 (3.2 mm) corner holes, independent of any host board's hole pattern. J2 must stay at the board edge for pogo-clip access during NVM programming; J1 (USB-C) needs an enclosure-wall cutout; keep J2/J3/J4 and the test points accessible and silkscreened for bring-up on whatever host this ends up in.

References

• Board Split Decision — Fix List + A/B Interface Contract (#90) — source of the fix list and the interface contract copied above

• v4 USB-PD Failure Diagnosis (#87) — root-cause analysis behind the D4/CC-termination fixes

• Spec-Architecture Review — the wave-5/wave-6 evidence review behind D8, the 22V/28V correction, and the 20V-reuse-guidance caveat above (findings BA-1 through BA-4)

• scripts/schgen/decisions.json and scripts/schgen/board_a_spec.py — the locked wave-6 decision record and the spec module that generates boards/board-a/board-a.kicad_sch

• NVM Programming Setup — full NVM programming procedure, hardware, and pitfalls

• STUSB4500 Pin Cheat-Sheet — per-pin rationale for U1

• Net-Table + Mermaid Convention — the documentation convention used above

• Bill of Materials — general JLCPCB fee structure and the (currently full single-board) BOM

• STUSB4500 (U1) is documented throughout this page; the Q1 load switch (AO3401A) gate network and J1 USB-C connector substitution options are documented above; SMAJ15A (cloned pattern for D5) is documented on Board B's Protection Stage; USBLC6-2SC6 (D4, removed) — see the deltas above for removal background

• .claude/skills/component-bzt52c11-c92321 — full primary-sourced evidence bundle for D8; generated component records index the validated evidence for every part on both boards