Board A — USB-PD Core

The small, cheap, reusable USB-PD 15V sink board (STUSB4500 + USB-C + load switch + NVM/debug pads) — the fixed circuit per the board-split decision (#90).

Board A is the USB-PD front end split out of the single-board zudo-pd design (epic #86). It negotiates a 15 V/3 A USB-PD contract with a STUSB4500, load-switches it, and hands the switched rail to Board B (the synth power stage) over a 6-pin cable connector. This page documents the fixed circuit — the front end after the board-split decision (#90) fix list is applied — not the failed v4 circuit described in v4 USB-PD Failure Diagnosis.

Purpose

• Cheap, re-orderable debug surface. The STUSB4500 front end was the source of two failed JLCPCB orders (v3's pin-18 bug, v4's CC-termination and D4-rating defects — see the diagnosis page). Splitting it onto its own small board means a bring-up failure only costs a re-spin of this board, not the whole multi-stage power supply.

• Reusable USB-PD 15 V sink module. Nothing on Board A or its output connector is synth-specific: it is a generic "negotiate 15 V over USB-PD, switch it, expose GND + two status flags" module, usable in any other project that needs a PD-negotiated DC rail.

• NVM-programmable. The same board carries the I2C pogo pads used to write the STUSB4500's PDO configuration — see NVM Programming Setup.

Block diagram

Net-connectivity table (fixed circuit)

Per Net-Table + Mermaid Convention. Derived from the 2026-07-05 kicad-cli sch export netlist export of the current usb-pd-input.kicad_sch sheet, with the #90 fix-list deltas applied on paper (D4 removed; R17/R18 DNP; R19/R20 rewired; D5-D7 added; J4 added as Board A's new A↔B interface connector — none of this was written back into the KiCad file).

Deltas vs the current single-board circuit

Board A's schematic is usb-pd-input.kicad_sch (the current single-board design) plus exactly these changes — the same list locked in board-split-decision.md §A6, items 1–5 (items 6–8 of that list are linear-regulation.kicad_sch/dc-dc-conversion.kicad_sch edits that belong to Board B, not Board A):

Removed

• D4 (USBLC6-2SC6, C7519) — deleted entirely, not relocated. Its VBUS-clamp role was a hard abs-max violation (6 V-rated zener on a 15 V rail); its CC-ESD role duplicated U1's own integrated 22 V-rated protection while adding a silent-failure class (candidate 3: CC continuity relying on a part-internal flow-through).

Set DNP (footprint kept, not populated, excluded from BOM/CPL)

• R17 / R18 (5.1 kΩ external Rd) — kept as rework insurance only. Fitting them in parallel with U1's own always-on internal 5.1 kΩ Rd puts the CC termination out of the USB Type-C sink window the moment U1 powers up (2.55 kΩ effective) — the v4 blocker.

Rewired

• R19 pin 2: GND → CC1 (restores CC1DB↔CC1 dead-battery termination, ST's reference topology for a VBUS-only sink).

• R20 pin 2: GND → CC2 (restores CC2DB↔CC2).

• CC1/CC2 connector-to-chip path: now direct copper (previously routed through D4's internal pin 1↔6 / 3↔4 flow-through).

Added

• D5 = SMAJ20A (SMA, unidirectional TVS), cathode on VBUS_IN, anode on GND. Clones the existing SMAJ15A_C571368 symbol/footprint pattern (used by TVS1/TVS3 on the linear-regulation sheet) into a new SMAJ20A_C571370 entry.

• D6 / D7 = Nexperia PESD24VS1UB (SOD-523), DNP, one per CC line to GND. Layout provision only — fit for enclosed/production builds, not the bring-up/debug build.

• J4 = the new Board A ↔ Board B interface connector (JST B6B-XH-A, 6-pin) — see below. This did not exist on the single-board design (the front end fed the DC-DC sheet directly through the shared VBUS_OUT net); Board A terminates that net at J4 instead.

Unchanged (re-confirmed correct, do not touch)

• Pin-18 network: VBUS_IN → R14 (470 Ω) → U1 pin 18 (the v3 fix).

• Q1 gate network (R11/R12/C35).

• VDD/VREG decoupling (C1/C2/C30/C34/C35).

• I2C NVM programming path (J2, R15/R16).

• Debug pogo block J3.

• Test points TP1/TP2/TP6.

Component list, LCSC parts, and rough cost

All LCSC part numbers below are read from the current schematic's netlist export (source of truth), not from the general BOM page, which has drifted on a few passive LCSC numbers since this front end was last exported. Prices are rough JLCPCB catalog estimates — re-verify at order time.

DNP (footprint only, not populated — no per-board cost):

Rough per-board total (fitted parts only): ~$2.85. U1 alone is ~88% of that — this is an inherent cost of the STUSB4500, not something Board A's split-out changes. What the split does change: this board has roughly a quarter of the single-board design's unique Extended-part count (U1, J1, J4, D5 vs. the full board's ~20), so JLCPCB's per-unique-part setup/Extended fees amortize much faster on a small reorder batch — the actual point of "cheap, re-orderable." Fabrication, stencil, setup, and Extended-part fees are separate from the component total above; see BOM for the general JLCPCB fee structure (those figures describe the full single-board order, not Board A alone).

A↔B interface contract (LOCKED — copied verbatim from #90)

Connector (both boards): JST B6B-XH-A(LF)(SN) — 6-pin top-entry shrouded THT header, 2.5 mm pitch, LCSC C144397 (genuine JST; stock listed 2026-07-05, re-verify at order time). Rated 3 A/contact (AWG #22), 250 V. Cable: commodity pre-crimped 6-way XH↔XH, AWG 22, 80–150 mm (or JST XHP-6 housings + SXH-001T-P0.6 contacts — verify stock at order time; cable-side parts are not on the PCBA BOM).

Current-rating math: worst case = PD contract cap 3.0 A @ 15 V (computed steady draw ≈2.5 A at the rated 26.5 W output budget). XH contact nameplate 3.0 A; 80% continuous derate → 2.4 A/contact. 2 contacts per power rail → 4.8 A derated capacity; at 3.0 A each contact carries 1.5 A = 50% of nameplate → 1.6× derated margin (2.0× nameplate). GND identical (2 contacts, symmetric return). Cable drop ≈16 mV round trip at 3 A (2× AWG 22 per leg, 100 mm) — negligible.

Keying/foolproofing: XH shrouded housing is mechanically polarized (reversed insertion blocked). Uniqueness rule: the 6-pin XH is the ONLY 6-position XH on either board. Pin 1 silkscreened on both boards.

Mechanical (LOCKED): side-by-side, cable-linked. Stacking rejected: USB-C must reach the enclosure wall, Board A's J2 pogo pads need face access for the NVM rig, Board B's TO-263 regulators need top-side copper/airflow, and a stack fixes relative orientation (hurts reuse). Each board carries its own 4× M3 (3.2 mm) mounting holes; no shared hole pattern.

Genericity: nothing synth-specific on the connector — 15 V power, GND, two generic open-drain status lines; a consumer that ignores pins 3–4 just gets switched 15 V.

On Board A, this connector is designated J4 (next free reference after J1 USB-C, J2 NVM pogo, J3 debug pogo) and carries VBUS_OUT (pins 1–2), ATT (pin 3), PDOK (pin 4), and GND (pins 5–6) per the net table above.

NVM programming interface, debug pads, and test points

J2 — NVM programming (pogo, 1×4, 2.54 mm)

Bare-copper pogo pads (no BOM cost), used with a pogo-pin clip and a NUCLEO-F072RB acting as a USB-to-I2C bridge. Full procedure, wiring, GUI steps, and pitfall table in NVM Programming Setup.

J3 — debug pads (pogo, 1×8, 2.54 mm)

Test points

Reuse guidance for other projects

Board A is designed to drop into any project that just needs a switched, PD-negotiated DC rail — not only this synth power supply.

Minimum wiring to reuse Board A standalone:

• Connect J4 pins 1–2 (VBUS_OUT) and pins 5–6 (GND) to the consuming circuit. That alone gives a plain switched-15 V sink module.

• Pins 3 (ATT) and 4 (PDOK) may be left unconnected — Board A negotiates and switches power on its own; nothing downstream needs to read these flags. If a consumer wants sequencing/fault info, pull each up externally (10–100 kΩ to a local rail ≤5 V) per the interface contract above.

NVM reconfiguration for other voltages: the negotiated voltage/current live entirely in the STUSB4500's NVM (see NVM Programming Setup), not in the schematic. A reuse project can reprogram J2 for a different PDO (e.g. 5 V, 9 V, 12 V, or 20 V, subject to the connected charger actually advertising it) instead of 15 V/3 A, without any hardware change — as long as D5's 20 V standoff and Q1's ratings (below) still cover the new target voltage. Reprogramming above 20 V nominal would need a higher-rated D5/Q1 and is out of scope for this board as documented.

Electrical limits to respect:

• VBUS_IN/VDD abs-max is 22 V (DS12499); D5 (SMAJ20A) is chosen with a 20 V standoff / 22.2–24.5 V breakdown / ≤32.4 V clamp specifically to sit under that ceiling with margin at the contracted 15 V, while still tolerating the 20 V-mis-contract edge case.

• Q1 (AO3401A) is rated −30 V/−4 A — comfortably above the 15 V/3 A design point.

• J4's 2 contacts per power rail give a 1.6× derated-current margin at the 3.0 A PD contract cap (see the current-rating math above); do not exceed that per-board 3 A cap when reusing Board A at higher currents without re-deriving the connector margin.

• A downstream circuit connected to VBUS_OUT must tolerate the ≤32.4 V transient clamp ceiling of D5 during a fault event, not just the nominal 15 V.

Mechanical: Board A carries its own 4× M3 (3.2 mm) corner holes, independent of any host board's hole pattern. J2 must stay at the board edge for pogo-clip access during NVM programming; J1 (USB-C) needs an enclosure-wall cutout; keep J2/J3/J4 and the test points accessible and silkscreened for bring-up on whatever host this ends up in.

References

• Board Split Decision — Fix List + A/B Interface Contract (#90) — source of the fix list and the interface contract copied above

• v4 USB-PD Failure Diagnosis (#87) — root-cause analysis behind the D4/CC-termination fixes

• NVM Programming Setup — full NVM programming procedure, hardware, and pitfalls

• STUSB4500 Pin Cheat-Sheet — per-pin rationale for U1

• Net-Table + Mermaid Convention — the documentation convention used above

• Bill of Materials — general JLCPCB fee structure and the (currently full single-board) BOM

• STUSB4500, AO3401A, USB-C connector, SMAJ15A (cloned pattern for D5), USBLC6-2SC6 (D4, removed — background only) — component reference pages