Board B — Synth Power Conversion

Design doc for Board B of the 2-board split — the DC-DC, LDO, protection, and Eurorack output stages that carry the expensive parts, fed by a stable 15 V from Board A.

Board B is the synth power conversion half of the 2-board split (epic #86). It receives a regulated 15 V from Board A (the USB-PD sink core) over a 6-pin cable and converts it into the modular-synth rails: +12 V/1.2 A, −12 V/0.8 A, +5 V/0.5 A. Board B carries every DC-DC converter, every linear regulator, all protection parts, and all output connectors — in other words, essentially all of the board's dollar cost and assembly complexity.

Role in the 2-Board Split

This project has failed USB-PD negotiation on four consecutive JLCPCB orders (v1–v4; see current status), and every failure traced back to the USB-PD front end, never to the DC-DC/LDO/protection circuitry documented here. Splitting the boards means the next debug iteration re-orders only the small, cheap board that actually keeps failing — see the cost comparison below.

Input: Board A ↔ Board B Interface Connector

Connector (both boards): JST B6B-XH-A(LF)(SN) — 6-pin top-entry shrouded THT header, 2.5 mm pitch, LCSC C144397 (genuine JST; stock listed 2026-07-05, re-verify at order time). Rated 3 A/contact (AWG #22), 250 V. Cable: commodity pre-crimped 6-way XH↔XH, AWG 22, 80–150 mm (or JST XHP-6 housings + SXH-001T-P0.6 contacts — verify stock at order time; cable-side parts are not on the PCBA BOM).

Current-rating math: worst case = PD contract cap 3.0 A @ 15 V (computed steady draw ≈2.5 A at the rated 26.5 W output budget). XH contact nameplate 3.0 A; 80% continuous derate → 2.4 A/contact. 2 contacts per power rail → 4.8 A derated capacity; at 3.0 A each contact carries 1.5 A = 50% of nameplate → 1.6× derated margin (2.0× nameplate). GND identical (2 contacts, symmetric return). Cable drop ≈16 mV round trip at 3 A (2× AWG 22 per leg, 100 mm) — negligible.

Keying/foolproofing: the XH shrouded housing is mechanically polarized (reversed insertion blocked). The 6-pin XH is the only 6-position XH on either board — Board B's Eurorack outputs are 2×8 shrouded IDC and the Faston tabs are physically incompatible, so the A↔B cable cannot land on a wrong header. Pin 1 is silkscreened on both boards.

Mechanical: side-by-side, cable-linked (stacking rejected — see the decision doc for the full rationale: USB-C enclosure access, Board A's NVM pogo-pad access, Board B's TO-263 top-side airflow, and reuse). Each board gets its own 4× M3 (3.2 mm) mounting holes; no shared hole pattern.

How the connector feeds Board B's existing circuitry

In boards/board-b/board-b.kicad_sch (generated from board_b_spec.py), the interface connector is J5 and its pins map onto Board B's carried-forward nets like this:

scripts/schgen/decisions.json): routed to P1, a PogoPad_1x04 bare-pad header (no fitted component, out of BOM) — pin 1 = ATT, pin 2 = PDOK, pin 3 = GND probe return, pin 4 = declared no-connect. Board B is power-only and has no logic to consume these flags; both signals are open-drain with no on-board pull-up on either board — any future consumer wired to P1 must supply its own pull-up to its own logic rail |

DC-DC Conversion Stage

Three LM2596S-ADJ (TO-263-5) converters, all fed from the shared +15 V input bus: two non-inverting bucks (U2, U3) and one inverting buck-boost (U4). Net connectivity below is from the current dc-dc-conversion.kicad_sch sheet, unchanged by the split.

Feedback dividers

All three recompute to their intended rail (formula per LM2596S-ADJ datasheet, Vout = 1.23 x (1 + Rtop/Rbottom), Vref = 1.23V). For U4, the IC's own GND pin bootstraps to the negative output (see below), so the divider's roles swap: the "bottom" resistor (R5, to system GND) and "top" resistor (R6, to the negative output) give the mirrored formula |Vout| = 1.23 x (1 + R5/R6).

Net tables

U2 — +13.5V buck

U3 — +7.5V buck

U4 — −13.5V inverting buck-boost

DC-DC stage topology

Linear Regulator (LDO) Stage

Three L78xx-family LDOs clean up the DC-DC outputs for <1mVp-p ripple. Dropout margins below are from Board B Architecture Review (#89), sourced against the L7812/L7805/CJ7912 datasheets.

Net tables (linear-regulation.kicad_sch)

Protection Stage

PTC resettable fuses plus TVS clamps on each output rail.

TVS polarity and connection rules

All three TVS positions use unidirectional parts, so orientation is functional, not cosmetic. The cathode is the marked end — the color band denotes it (fact-smaj15a-polarity).

TVS3 is the reversed one, and that reversal is a locked spec point rather than a layout preference: decision tvs3-orientation (scripts/schgen/decisions.json) requires board_b_spec.py to carry it as explicit pin-to-net rows, which it does — TVS3.1 on GND, TVS3.2 on -12V rail. Fitted the other way round, a unidirectional TVS on a negative rail is forward-biased at −12 V: a dead short through one diode drop across the rail, from the moment the board powers up. Nothing was wrong before this lock — the orientation had simply never been captured by any spec artifact (finding BB-9), which is precisely the state in which an assembly error goes unnoticed.

Correctly oriented, TVS3 stands off 15 V against the rail's 12.0 V nominal — 3 V / 25 % margin (fact-smaj15a-margin-plus12, fact-smaj15a-margin-percent) — and its 16.7 V breakdown minimum stays 4.1 V above 12.6 V, the band-edge proxy used for the CJ7912-fed −12 V rail (fact-l7812cd2t-vout-band's 12.6 V maximum, borrowed as the magnitude proxy since no equivalent band is retained for the CJ7912).

TVS placement and verification

A TVS only clamps what it sits next to: trace inductance between the transient and the diode develops its own voltage, so a correctly chosen part placed far from the load still lets the spike through.

1. Place each TVS as close to the protected load as the layout allows.

2. Short, wide traces — parasitic inductance of that path is the quantity being minimized.

3. Anode straight to the ground plane, with a short low-impedance return.

4. TVS goes after the PTC in the chain, matching the Net-(U6-OUT) -> PTC1 -> +12V rail -> TVS1.1 ordering in board_b_spec.py.

No heatsinking is needed at any of the three positions. Steady-state dissipation is ≈75 µW (15 V × the 5 µA leakage maximum, fact-smaj15a-leakage) and lower still at the 12 V rail; the 400 W figure (fact-smaj15a-pppm) is peak pulse power on a 10/1000 µs waveform, and the SMA package's own thermal mass covers events that brief. Repetitive surges are a different question — consult the datasheet derating curves if the application sees them.

Bench verification, per fitted part:

Full clamping verification needs a surge generator and is out of scope for a bench bring-up.

Choosing a different SMAJ standoff

Only the SMAJ15A row is primary-sourced in this project's evidence base (fact-smaj15a-standoff, fact-smaj15a-breakdown, fact-smaj15a-clamp). The sibling rows are family reference values and must be re-confirmed against the specific manufacturer's datasheet before any of them is fitted.

Selection rule: working voltage × 1.2, then take the next standoff up. A 12 V rail wants 14.4 V and lands on SMAJ15A; a 15 V rail wants 18 V and lands on SMAJ18A. Note that the clamp voltage rises with the standoff, so take the lowest standoff that still clears the rail's own upper band edge — every extra volt of standoff is an extra volt the downstream parts must survive during a real event. TVS2's replacement (decision (a)) is this rule applied on the +5 V rail: SD05's 5 V standoff sat exactly at the rail's nominal and below the L7805's guaranteed 5.2 V band top, so it could conduct during normal regulation.

PTC1 and the L7812 current-limit cascade

The design intent worth recording is that PTC1 is a backstop, not the primary limiter. The two protections work on different timescales: a linear regulator's current limit is electronic and acts essentially at once, with thermal shutdown following as the die heats, whereas a PTC is a thermal device that must warm for seconds before it trips. U6 therefore reacts first, and in ordinary fault handling PTC1 rarely reaches its trip point at all. It exists for the case where U6's own protection is bypassed or defeated — a shorted pass element, or a fault that does not route through the regulator.

The PTC1 column below is sourced (fact-ptc1b-ihold, fact-ptc1b-itrip); the U6 column deliberately states no threshold, for the reason in the warning that follows.

PTC1 voltage drop and acceptance testing

A PTC's series resistance shows up directly as output droop, so it is a budget item, not a free protection layer. The fitted part's resistance is not in the evidence base: SMD1210P150TF/16 (C7529589) has confirmed hold, trip, and voltage figures but no retained initial or post-trip resistance. The C20808 sibling's numbers (Ri min 0.015 Ω, R1 max 0.07 Ω) belong to a different part and must not be substituted for it. The drop is therefore a bench measurement, and this is the gate:

Two numbers are worth tracking over the board's life, because PTC resistance rises with trip cycles: the normal-operation drop (a growing drop is the wear indicator) and the reset time after a trip. Separately, fact-ptc1b-hold-85c records that no 85 °C-derated hold figure is retained for the /16 variant, so hot-enclosure hold current is another bench item — the same class of open question already flagged for PTC3 (finding BB-8).

PTC1 failure modes

Wear-out — the normal one. After many trip cycles the initial resistance creeps up, hold current drifts down, and trip time lengthens. The part still protects, at degraded specs. It surfaces as a slower reset and a larger normal-operation voltage drop, which is why that drop is the number to track.

Stuck open — rare. The +12 V rail goes dead with no backup on that rail. The symptom is unambiguous (no +12 V at J7 or the Eurorack headers) and the fix is replacing PTC1.

Stuck closed — rarer. PTC1 stops protecting, but it is the outermost of four layers, not the only one: U6's current limiting, U6's thermal shutdown, U2's LM2596S-ADJ current limiting, and the USB-PD source's own protection all remain. This is the failure mode that matters least — which is the same point the cascade above makes from the other direction.

PTC2 hold-current rationale on the +5 V rail

PTC2 (mSMD110-33V, C70119) holds at 1.10 A and trips at 2.20 A (fact-ptc2-ihold, fact-ptc2-itrip) on a rail budgeted at 0.5 A, so the hold current sits 1.1 A / 0.5 A = 2.2× above the budget. The gap is deliberate:

• 0.5 A is the specified rail budget, so a 1.1 A hold leaves better than 2× headroom for power-on surge and brief spikes without nuisance trips.

• A sustained draw above 1.1 A trips PTC2 rather than pushing U7 or the +7.5 V DC-DC stage into their own limits — the PTC, not the regulator, sets the ceiling here.

• 33 V against a 5 V rail is 28 V of voltage margin (fact-ptc2-vmax-margin), so this position carries none of the voltage-rating exposure that made PTC1's original part a blocker.

Output Connectors

J6–J9 — Faston rail terminals

Unambiguous 1:1 rail assignment — each Faston terminal's two tabs are tied to the same net.

Mating connectors

The fitted part (TE 63951-1, LCSC C591344) is a FASTON 250 tab — 6.35 mm × 0.8 mm blade, right-angle THT (fact-faston-tab-dimensions) — so it mates with standard FASTON 250 receptacles:

Prefer fully-insulated crimp receptacles on 18 AWG for the lowest resistance and the most current capacity. Cable-side parts are not on the PCBA BOM.

Why a single GND terminal is enough

J9 is the only GND return for all three rails, which looks under-provisioned next to three separate supply tabs. It is not:

1. In a Eurorack system every module's GND lands on the busboard anyway — the busboard already commons all of them, so a second board-side GND tab buys nothing electrically.

2. Worst-case combined return is the sum of the three rail budgets, 1.2 A + 0.8 A + 0.5 A = 2.5 A — and that sum is itself conservative, since the ±12 V returns partly cancel in practice.

3. Fewer terminals means less wiring and fewer crimps to get wrong.

4. It matches how common Eurorack busboard designs are wired.

J10/J11 — 2×8 Eurorack power headers

This matches the community-standard Doepfer/Eurorack 16-pin power-header convention. The exact physical key/polarization-slot orientation of the 2541WR-2X08P footprint (whether pin 1 truly sits under the red-stripe cable convention) is not verifiable from the netlist — confirm against the footprint silkscreen or a physical board before finalizing Board B's layout.

Output stage topology

Bill of Materials and Cost Split

Board B carries essentially all of the design's dollar cost and assembly complexity. Figures below are the existing single-board BOM's per-stage subtotals, remapped onto the split.

Component subtotal by board

Both boards additionally carry one A↔B interface connector (JST B6B-XH-A, LCSC C144397, a few cents each) — negligible next to the totals above.

Why the expensive parts land on Board B

U1 (STUSB4500) is Board A's single priciest part, but Board B still carries ~1.7× Board A's total component cost — and, more importantly for manufacturing cost, nearly all of the design's physically large/hand-solder- candidate parts (electrolytics up to 10.2mm tall, THT Faston tabs, THT 2×8 headers) and distinct Extended-part-fee line items (JLCPCB charges ¥470 per unique Extended part number, one-time — see BOM).

Why split: debug-iteration cost comparison

This project has needed four re-orders so far (v1–v4), and every failure has been in the USB-PD front end — never in the DC-DC/LDO/protection circuitry this doc covers. Under the current single, combined board, every one of those re-orders paid for the entire board:

Design Notes from the #89 Architecture Review

Every finding from Board B Architecture Review (#89) carried into this doc, with its locked disposition from Board Split Decision (#90, section A5):

References

• Board Split Decision (#90) — the locked A↔B interface contract and the #89 finding dispositions this doc implements

• Board B Architecture Review (#89) — full DC-DC/LDO/protection/output review this doc's stage sections summarize

• Spec-Architecture Review — the wave-5 evidence review behind the PTC1/TVS2/C5-C7/C4-C22-C23 part-swap decisions above (findings BB-1, BB-2, BB-6)

• scripts/schgen/decisions.json and scripts/schgen/board_b_spec.py — the locked wave-6 decision record and the spec module that generates boards/board-b/board-b.kicad_sch

• generated component records — validated evidence for every part on both boards, projected from the component skill bundles

• Bill of Materials — full single-board parts list, prices, and the JLCPCB Extended-parts fee structure referenced in the cost split above

• Mechanical Design — component heights driving Board B's enclosure/heatsink design

• Circuit Diagrams — schemdraw-generated diagrams for the DC-DC (D2/D3/D4) and LDO (D5/D6/D7) stages, still valid for Board B

• Net-Table + Mermaid Convention — the documentation convention followed above

• Board A (USB-PD core) design doc — overview/board-a-usb-pd-core.md (sibling doc, #91)