Board B — Synth Power Conversion
Design doc for Board B of the 2-board split — the DC-DC, LDO, protection, and Eurorack output stages that carry the expensive parts, fed by a stable 15 V from Board A.
Board B is the synth power conversion half of the 2-board split (epic #86). It receives a regulated 15 V from Board A (the USB-PD sink core) over a 6-pin cable and converts it into the modular-synth rails: +12 V/1.2 A, −12 V/0.8 A, +5 V/0.5 A. Board B carries every DC-DC converter, every linear regulator, all protection parts, and all output connectors — in other words, essentially all of the board's dollar cost and assembly complexity.
Note
This doc documents the circuitry as it will exist on Board B's own KiCad project, once laid out. No new KiCad project exists yet — that is the nextplan (see epic #86 "Non-goals"). The stage-level net tables below are derived from the existing, still-combined zudo-pd.kicad_sch netlist (the DC-DC, LDO, protection, and output sheets are unchanged by the split and carry forward into Board B as-is), exported with:
kicad-The A↔B interface connector itself is new — it does not exist in the netlist yet — so its section below documents the locked contract directly rather than a netlist export.
Role in the 2-Board Split
| Board A (USB-PD core) | Board B (this doc) | |
|---|---|---|
| Carries | STUSB4500, USB-C receptacle, load switch, NVM programming pads | DC-DC converters, LDOs, protection, Eurorack + Faston outputs |
| Reusable elsewhere | Yes — generic "USB-PD 15 V sink module" | No — synth-specific rails and connectors |
| Component cost | Low (~0.45, dominated by one 2.50 IC) | High (~$3.51 — see Bill of Materials and Cost Split) |
| Re-order cost when it fails | Small board, few Extended parts | Larger board, most of the design's Extended-part and hand-solder load |
This project has failed USB-PD negotiation on four consecutive JLCPCB orders (v1–v4; see current status), and every failure traced back to the USB-PD front end, never to the DC-DC/LDO/protection circuitry documented here. Splitting the boards means the next debug iteration re-orders only the small, cheap board that actually keeps failing — see the cost comparison below.
Input: Board A ↔ Board B Interface Connector
Warning
The pinout table below is copied exactly from the locked spec inBoard Split Decision (#90, section "Decision set (b)") and from sub-issue #92's own locked-spec block, so it is byte-identical to the copy in the Board A doc (overview/). Do not edit the table's wording — wave-4 (#95) diff-checks both copies against each other and against the decision doc.
Connector (both boards): JST B6B-XH-A(LF)(SN) — 6-pin top-entry shrouded THT header, 2.5 mm pitch, LCSC C144397 (genuine JST; stock listed 2026-07-05, re-verify at order time). Rated 3 A/contact (AWG #22), 250 V. Cable: commodity pre-crimped 6-way XH↔XH, AWG 22, 80–150 mm (or JST XHP-6 housings + SXH-001T-P0.6 contacts — verify stock at order time; cable-side parts are not on the PCBA BOM).
| Pin | Signal | Direction | Notes |
|---|---|---|---|
| 1 | +15V | A → B | Board A VBUS_OUT (post Q1 load switch), PD-contract 15 V |
| 2 | +15V | A → B | Paired with pin 1 (current sharing) |
| 3 | ATT | A → B, open-drain, active-low | STUSB4500 pin 11 (ATTACH). No pull-up on Board A; Board B (or any host) pulls up 10–100 kΩ to a local rail ≤5 V if used. May be left unconnected |
| 4 | PDOK | A → B, open-drain, active-low | STUSB4500 pin 20 (POWER_OK2): asserts when the PDO2 (15 V) contract is live. Same pull-up rule as ATT. May be left unconnected |
| 5 | GND | — | Paired return |
| 6 | GND | — | Paired return |
Current-rating math: worst case = PD contract cap 3.0 A @ 15 V (computed steady draw ≈2.5 A at the rated 26.5 W output budget). XH contact nameplate 3.0 A; 80% continuous derate → 2.4 A/contact. 2 contacts per power rail → 4.8 A derated capacity; at 3.0 A each contact carries 1.5 A = 50% of nameplate → 1.6× derated margin (2.0× nameplate). GND identical (2 contacts, symmetric return). Cable drop ≈16 mV round trip at 3 A (2× AWG 22 per leg, 100 mm) — negligible.
Keying/foolproofing: the XH shrouded housing is mechanically polarized (reversed insertion blocked). The 6-pin XH is the only 6-position XH on either board — Board B's Eurorack outputs are 2×8 shrouded IDC and the Faston tabs are physically incompatible, so the A↔B cable cannot land on a wrong header. Pin 1 is silkscreened on both boards.
Mechanical: side-by-side, cable-linked (stacking rejected — see the decision doc for the full rationale: USB-C enclosure access, Board A's NVM pogo-pad access, Board B's TO-263 top-side airflow, and reuse). Each board gets its own 4× M3 (3.2 mm) mounting holes; no shared hole pattern.
How the connector feeds Board B's existing circuitry
Once laid out, the interface connector's pins map onto Board B's carried- forward nets like this:
| Connector pin(s) | Board B net (post-split) | Today's net (in the still-combined schematic) |
|---|---|---|
| 1, 2 (+15V) | Board B's local +15 V input rail | +15V -> +13.5V gen — the shared bus already feeding U2.1 U3.1 U4.1 (see DC-DC Conversion Stage) |
| 5, 6 (GND) | Board B's local GND plane | GND — the existing system ground net |
| 3 (ATT), 4 (PDOK) | Not connected by default | New signals; Board B is power-only and has no logic to consume them. Provision as an unpopulated 2-pin test header for a future add-on (e.g. a status LED daughterboard) rather than wiring them anywhere on the power path |
Info
The DC-DC input bus net is literally named +15V -> +13.5V gen in the existing netlist — a leftover label from when U2 was the only thing on it (seeBoard B Architecture Review §2). It already fans out to all three DC-DC converters, so Board B's layout simply renames/re-derives this bus from the new connector instead of from the old USB-PD sheet.
DC-DC Conversion Stage
Three LM2596S-ADJ (TO-263-5) converters, all fed from the shared +15 V input
bus: two non-inverting bucks (U2, U3) and one inverting buck-boost (U4). Net
connectivity below is from the current dc-dc-conversion.kicad_sch sheet,
unchanged by the split.
Feedback dividers
| Converter | Rail | Top resistor (to output) | Bottom resistor (to GND) | Feedforward cap | Formula result |
|---|---|---|---|---|---|
| U2 | +13.5V | R1 = 10k → FB | R2 = 1k, FB → GND | C31 (22nF) across R1 | 1. |
| U3 | +7.5V | R3 = 5.1k → FB | R4 = 1k, FB → GND | C32 (22nF) across R3 | 1. |
| U4 | −13.5V (inverting) | R6 = 1k, FB → −13.5V OUT | R5 = 10k, FB → GND | C33 (22nF) across R5 | 1. (mirrored divider — see note below) |
All three recompute to their intended rail (formula per LM2596S-ADJ
datasheet, Vout =, Vref = 1.23V). For U4, the IC's
own GND pin bootstraps to the negative output (see below), so the divider's
roles swap: the "bottom" resistor (R5, to system GND) and "top" resistor (R6,
to the negative output) give the mirrored formula
|Vout| =.
Net tables
U2 — +13.5V buck
| Net | Connected pins (Ref.Pin) | Value/Note |
|---|---|---|
+15V -> +13.5V gen | U2.1 C5.1 C6.1 (+ U3.1, U4.1 shared) | +15V input from Board A via the A↔B connector |
Net-(D1-K) | U2.2 D1.1 L1.1 | Switch node |
/ | L1.2 R1.2 C3.1 C31.2 (+ C14.1 C20.1 U6.1(IN) on the LDO sheet) | +13.5V DC-DC output (U2's switch node reaches this net through L1); feeds U6 (L7812) |
Net-(U2-Feedback) | U2.4 R1.1 R2.2 C31.1 | FB divider midpoint |
GND | U2. | Always-enabled (ON/OFF tied to GND) |
U3 — +7.5V buck
| Net | Connected pins (Ref.Pin) | Value/Note |
|---|---|---|
+15V -> +13.5V gen | U3.1 C7.1 C8.1 (shared bus) | +15V input |
Net-(D2-K) | U3.2 D2.1 L2.1 | Switch node |
/ | L2.2 R3.1 C4.1 C32.2 (+ C15.1 C22.1 U7.1(IN) on the LDO sheet) | +7.5V DC-DC output (U3's switch node reaches this net through L2); feeds U7 (L7805) |
Net-(U3-Feedback) | U3.4 R3.2 R4.1 C32.1 | FB divider midpoint |
GND | U3. | Always-enabled |
U4 — −13.5V inverting buck-boost
| Net | Connected pins (Ref.Pin) | Value/Note |
|---|---|---|
+15V -> +13.5V gen | U4.1 C9.1 C10.1 (shared bus) | +15V input |
Net-(D3-K) | U4.2 D3.1 L3.1 | Switch node |
/ | U4. (+ C16.1 C24.2 U8.2(VIN) on the LDO sheet) | U4's own GND pin, ON/OFF, and TAB all bootstrap to −13.5V (not system GND) — feeds U8 (CJ7912) |
Net-(U4-Feedback) | U4.4 R5.1 R6.1 C33.1 | FB divider midpoint |
GND (system) | L3.2 only | Inductor references system GND (inverting topology: inductor switch-node→GND, catch diode switch-node→output — opposite of U2/U3's buck arrangement) |
DC-DC stage topology
Linear Regulator (LDO) Stage
Three L78xx-family LDOs clean up the DC-DC outputs for <1mVp-p ripple. Dropout margins below are from Board B Architecture Review (#89), sourced against the L7812/L7805/CJ7912 datasheets.
| LDO | Rail | Intermediate → output | Available margin | Datasheet dropout (typ) | Actual load | Verdict |
|---|---|---|---|---|---|---|
| U6 L7812 | +12V | 13.5V → 12V | 1.5V | 2.0V @ IO = 1A | 1.2A | Open item — see below |
| U7 L7805 | +5V | 7.5V → 5V | 2.5V | 2.0V @ IO = 1A | 0.5A | OK — real dropout at half the test current expected well under 2.0V |
| U8 CJ7912 | −12V | −13.5V → −12V | 1.5V | 1.1V @ Io = 1A | 0.8A | OK, thinner margin than +5V — worth a bench check at full load |
L7812 dropout — open design item, deferred to the Board B design plan
The datasheet's own typical dropout (2.0V, measured at 1A) already exceeds the 1.5V available on this board — and the actual load (1.2A) is higher than the 1A test point, where dropout is worse, not better. This is not resolved here; per the #90 decision (disposition A5#1) it is explicitly deferred, bench-gated:
Gate: bench-measure a real L7812 at 1.2A from a 13.5V source before Board B's layout is frozen.
Preferred direction if confirmed: raise the +13.5V intermediate rail (e.g. R1 10k → 11k gives 14.76V). This raises U6's dissipation from ~1.8W to ~3.3W, so the final setpoint is locked together with Board B's thermal budget (heatsinking, TO-263 copper pour), not before.
Fallback: swap U6 for a lower-dropout regulator.
Do not silently "fix" this by picking a rail voltage in this doc — the numeric setpoint is a Board B design-phase decision, not a documentation decision.
Net tables (linear-regulation.kicad_sch)
| Net | Connected pins (Ref.Pin) | Value/Note |
|---|---|---|
/ (relevant) | C14.1 C20.1 U6.1(IN) | +12V LDO input |
Net-(U6-OUT) | U6.3(OUT) C17.2 C21.1 R7.1 PTC1.1 | +12V LDO output, before PTC1 |
/ (relevant) | C15.1 C22.1 U7.1(IN) | +5V LDO input |
Net-(U7-OUT) | U7.3(OUT) C18.1 C23.1 R8.1 PTC2.1 | +5V LDO output, before PTC2 |
/ (relevant) | C16.1 C24.2 U8.2(VIN) | −12V LDO input |
Net-(U8-OUT) | U8.3(OUT) C19.1 C25.2 R9.1 PTC3.1 | −12V LDO output, before PTC3 |
GND (relevant) | C14.2 C15.2 C17.1 C18.2 C20.2 C21.2 C22.2 C23.2 U6.4 U7.2 U8.1 | +12V/+5V decoupling references GND individually (see below for the −12V network's corrected form) |
Negative-rail decoupling — fixed in #93, document the corrected network
The as-designed −12V decoupling network (C16/C19/C24/C25) has a genuine missing-GND defect: today's netlist still shows all four caps' far plates tied to each other on an isolated node (Net-(C16-Pad2)), not to GND — unlike the mirrored +12V/+5V networks, where the equivalent far plates connect individually to GND. Per the #90 decision (A5#2), this is fixed in #93by merging Net-(C16-Pad2) into GND (C16.2, C24.1, C19.2, C25.1 all become GND members). Board B's design should carry forward the correctednetwork — i.e. C16.2/C24.1 and C19.2/C25.1 route straight to GND, matching the +12V/+5V pattern — not the network as it appears in today's still-unfixed netlist.
Protection Stage
PTC resettable fuses plus TVS clamps on each output rail.
| Ref | Part (LCSC) | Hold current | Voltage rating | Rail | Rated load | Margin | Status |
|---|---|---|---|---|---|---|---|
| PTC1 | SMD1210P200TF (C20808) | 2.00A hold / 4.00A trip | not confirmed from available sources | +12V | 1.2A | 1.67× | Confirm against RUILON's datasheet at order time (open data gap, #89 lead 5a) |
| PTC2 | mSMD110-33V (C70119) | 1.10A hold | 33V | +5V | 0.5A | 2.2× | OK |
| PTC3 | BSMD1206-150-16V (C883133) | 1.50A hold | 16V | −12V | 0.8A | 1.875× | OK |
| TVS1 | SMAJ15A (C571368) | — | VRWM 15V, clamp 24.4V @ 1A | +12V | — | 25% standoff headroom | OK |
| TVS3 | SMAJ15A (C571368) | — | same as TVS1 | −12V | — | 25% standoff headroom | OK |
| TVS2 | SD05 (C502527) | — | VRWM 5V | +5V | — | 0% standoff headroom | Deferred to Board B design phase — see below |
TVS2 — deferred to Board B design phase
VRWM = 5V sits exactly at the +5V rail's nominal voltage — zero standoff margin — and the L7805's own datasheet allows the output to reach 5.2V under normal operation, already above TVS2's rated standoff. Per the #90 decision, this is not included in the #93 KiCad fix; it is deferred to Board B's own design phase. Direction: replace TVS2 with a ≥6V-standoff part (e.g. an SD6.5-class device) so the L7805's legal 4.8–5.2V output window never sits at or above the TVS's VRWM.
Output Connectors
J6–J9 — Faston rail terminals
| Ref | Net | Signal |
|---|---|---|
| J6 | -12V rail | −12V |
| J7 | +12V rail | +12V |
| J8 | +5V rail | +5V |
| J9 | GND | GND |
Unambiguous 1:1 rail assignment — each Faston terminal's two tabs are tied to the same net.
J10/J11 — 2×8 Eurorack power headers
| Pin(s) | Net | Note |
|---|---|---|
| 1–2 | GATE rail | Isolated stub — power-only board, nothing else on this net |
| 3–4 | CV rail | Isolated stub |
| 5–6 | +5V rail | |
| 7–8 | +12V rail | |
| 9–14 | GND | Six-pin GND "moat" separating +12V from −12V |
| 15–16 | -12V rail | Far end from CV/Gate/+5V — a one-pin connector misalignment lands on GND, never on +12V/−12V or a signal line |
This matches the community-standard Doepfer/Eurorack 16-pin power-header
convention. The exact physical key/polarization-slot orientation of the
2541WR-2X08P footprint (whether pin 1 truly sits under the red-stripe
cable convention) is not verifiable from the netlist — confirm against the
footprint silkscreen or a physical board before finalizing Board B's layout.
Output stage topology
Bill of Materials and Cost Split
Board B carries essentially all of the design's dollar cost and assembly complexity. Figures below are the existing single-board BOM's per-stage subtotals, remapped onto the split.
Component subtotal by board
| Board | Stages carried | Component subtotal | Source |
|---|---|---|---|
| Board A | USB-PD (STUSB4500, load switch, USB-C receptacle, ESD/TVS, resistors/caps) | ~$0.45 | BOM Stage 1 |
| Board B | DC-DC (2.09) + LDO (0.37) + Protection (0.77) + Output (0.28) | ~$3.51 | BOM Stages 2–5 |
Both boards additionally carry one A↔B interface connector (JST B6B-XH-A, LCSC C144397, a few cents each) — negligible next to the totals above.
Why the expensive parts land on Board B
| Category | Parts | Unit price | Qty | Board |
|---|---|---|---|---|
| USB-PD controller | U1 STUSB4500QTR | $2.50 | 1 | A |
| Power inductors, 100µH/4.5A | L1, L2, L3 | $0.378 | 3 | B |
| DC-DC converter ICs (TO-263-5) | U2, U3, U4 LM2596S-ADJ | $0.266 | 3 | B |
| Bulk electrolytics, 470µF (25V/35V) | C3, C11, C14, C20, C21, C24, C25 | $0.04 | 7 | B |
| Bulk electrolytics, 470µF (16V) | C4, C22, C23 | $0.05 | 3 | B |
| LDO regulators (TO-263-2 / TO-252) | U6 L7812, U7 L7805, U8 CJ7912 | $0.11 | 3 | B |
| Faston power terminals | J6–J9 | ~$0.26 | 4 | B |
| 2×8 Eurorack headers | J10, J11 | ~$0.08 | 2 | B |
| USB-C receptacle | J1 | $0.05 | 1 | A |
| Load-switch MOSFET | Q1 AO3401A | $0.02 | 1 | A |
U1 (STUSB4500) is Board A's single priciest part, but Board B still carries ~8× Board A's total component cost — and, more importantly for manufacturing cost, nearly all of the design's physically large/hand-solder- candidate parts (electrolytics up to 10.2mm tall, THT Faston tabs, THT 2×8 headers) and distinct Extended-part-fee line items (JLCPCB charges ¥470 per unique Extended part number, one-time — see BOM).
Why split: debug-iteration cost comparison
This project has needed four re-orders so far (v1–v4), and every failure has been in the USB-PD front end — never in the DC-DC/LDO/protection circuitry this doc covers. Under the current single, combined board, every one of those re-orders paid for the entire board:
| Single combined board (current) | Split — Board A only re-ordered | |
|---|---|---|
| Extended parts re-paid | A handful — STUSB4500, USB-C receptacle, the shared A↔B connector (roughly 3–4 unique Extended parts) | |
| Hand-solder / THT candidates re-paid | Faston terminals, 2×8 headers, tall electrolytics — none of which were the bug | None of these exist on Board A |
| PCB fabrication + stencil | Full-size board | Small board (front-end only) |
| Reference single-unit total (from BOM) | ~¥16,500 for 1 board | Order-of-magnitude estimate: ~¥3,000–5,000 for 1 board, given roughly 3–4 of ~20 Extended parts and a much smaller PCB |
Note
The Board-A-only figure is an illustrative, order-of-magnitude estimate, not a quote — Board A's actual layout, part count, and size are not finalized yet (that is the next plan, per epic #86's "Non-goals"). The point the split is designed to prove is qualitative and robust regardless of the exact multiplier: a USB-PD-only debug iteration (the failure mode this project has hit on every revision to date) no longer has to re-pay for inductors, LDOs, electrolytics, and connectors that were never the problem.
Design Notes from the #89 Architecture Review
Every finding from Board B Architecture Review (#89) carried into this doc, with its locked disposition from Board Split Decision (#90, section A5):
| Finding | Disposition | Status |
|---|---|---|
| U6 (L7812) dropout margin: 1.5V available < 2.0V typ dropout at a lower test current than the actual 1.2A load | Deferred to the Board B design plan, bench-gated | Open — see Linear Regulator Stage |
U8 (CJ7912) −12V decoupling network's Net-(C16-Pad2) missing its GND tie | Fixed in #93 | Resolved — document the corrected network (see Linear Regulator Stage) |
| C9 (100µF, 25V rated) bridges +15V to −13.5V = 28.5V nominal (33.5V @ 20V edge case), over its own rating | Fixed in #93 — swapped to DMBJ RVT1H101M0810, 100µF 50V, LCSC C970687 (alt: Semtech CK1H101M-CRF10, C129420); can grows to 8×10.2mm | Resolved — Board B gets a fresh layout anyway, so the footprint change is free |
| TVS2 (SD05) zero standoff margin on the +5V rail | Deferred to Board B design phase | Open — see Protection Stage |
C4/C22/C23 Value field says "16V" but the actual LCSC part (RVT1A471M0607/C335982) is 10V-rated | Fixed in #93 — Value field corrected to 470uF 10V (electrically safe on the 7.5V/5V nets either way) | Resolved — data-integrity only, no netlist change |
| PTC1 voltage rating not confirmed from available sources | Unresolved data gap | Open — confirm against RUILON's datasheet at order time |
| U4 inverting buck-boost referencing (GND/ON-OFF/TAB bootstrap, D3/L3 orientation) | OK-confirmed, no action | Carried forward unchanged |
| C5/C7 input-cap margin at the 20V edge case (20% headroom) | Lead-to-verify, no fix scheduled | Open — worth re-checking once Board B's own input-margin policy is set |
| J10/J11 Eurorack header structure (GND moat, −12V placement) | OK-confirmed (structure); physical key orientation not netlist-verifiable | Carried forward — verify key orientation against the footprint/physical board before Board B layout is finalized |
References
Board Split Decision (#90) — the locked A↔B interface contract and the #89 finding dispositions this doc implements
Board B Architecture Review (#89) — full DC-DC/LDO/protection/output review this doc's stage sections summarize
Bill of Materials — full single-board parts list, prices, and the JLCPCB Extended-parts fee structure referenced in the cost split above
Mechanical Design — component heights driving Board B's enclosure/heatsink design
Circuit Diagrams — schemdraw-generated diagrams for the DC-DC (D2/D3/D4) and LDO (D5/D6/D7) stages, still valid for Board B
Net-Table + Mermaid Convention — the documentation convention followed above
Board A (USB-PD core) design doc —
overview/(sibling doc, #91)board- a- usb- pd- core. md