Bill of Materials (BOM)

Complete parts configuration for JLCPCB SMT assembly, across both boards of the two-board split.

Every reference designator, value, and LCSC number on this page is read from the two schgen spec modules — scripts/schgen/board_a_spec.py and scripts/schgen/board_b_spec.py — which are the source of truth for boards/board-a/board-a.kicad_sch and boards/board-b/board-b.kicad_sch. Part swaps carry the decision key from scripts/schgen/decisions.json that locked them.

Stage-to-Board Map

The JST B6B-XH-A interface connector appears on both boards — J4 on Board A, J5 on Board B. See the A↔B interface contract.

Power Supply Specifications

Rail budgets (the currents this design is sized for, per CLAUDE.md):

Total output budget: 12 V × 1.2 A + 5 V × 0.5 A + 12 V × 0.8 A = 26.5 W.

• Input: USB-C PD 15 V, 3 A contract

• Efficiency: ~75-80% — a design estimate, not a measurement

Stage 1: USB-PD Voltage Acquisition (Board A)

Source: scripts/schgen/board_a_spec.py. The full design rationale for this stage is on the Board A: USB-PD Core page; the table below is the parts list only.

Main ICs, connector, and protection

Capacitors

Resistors

DNP provisions (footprint placed, not populated, excluded from BOM/CPL)

Zero-cost pads

Stage 1 subtotal: ~$2.90 (fitted parts only, J4 included). U1 alone is ~86% of it. Matches the itemized figure on Board A → Component list.

Key features (STUSB4500 vs the v1.0 CH224D design):

Critical notes:

• Load switch (Q1) controls the power path — it only conducts after successful PD negotiation

• VBUS_EN_SNK (U1.16, active-low, open-drain) pulls LOW on success, turning Q1 ON

• Soft-start via C35 limits inrush: τ = R12 × C35 = 56 kΩ × 100 nF = 5.6 ms

• NVM programming is required to configure the 15 V PDO (one-time setup), and must be done before first attach to a 20 V-capable source. D8 is the hardware guard for the case where it is not — see Board A → Programming order and the D8 gate clamp

Stage 2: DC-DC Converters (Board B)

Three LM2596S-ADJ: U2 and U3 as buck converters, U4 in an inverting buck-boost configuration. There is no LM2586 and no SEPIC anywhere in this design — decision (b) in scripts/schgen/decisions.json locks that wording against the schematic.

Main ICs

Inductors

Diodes

All three catch/freewheeling positions are the same SS34, LCSC C8678. An "SS36, 60 V" figure circulated for D3 in older revisions of the circuit-diagram page; the fitted part is the 40 V SS34 at every position.

Feedback resistors

R1 stays 10 kΩ by decision (f): the +13.5 V setpoint's dropout margin against U6 is recorded as an open bench item, not changed on paper.

Electrolytic capacitors

Ceramic capacitors (DC-DC stage)

Stage 2 subtotal: ~$2.28 (includes the C9 estimate and C12, added by decision neg-rail-cap-bank).

Stage 3: Linear Regulators (Board B)

Regulator ICs

Ceramic input capacitors (470 nF)

U6 has no 470 nF ceramic on its input, unlike U7 and U8. The bypass parts board_b_spec.py places on the +13.5V OUT net alongside U6.1 are C14.1 and C20.1 — two 470 µF / 35 V electrolytics — with the rest of that net being U2's own output filter (C3.1), the feedback network (R1.2, C31.2), and the TP3 test pad. That asymmetry against U7/U8 is real, not a documentation gap.

Ceramic output capacitors (100 nF)

Large electrolytic capacitors (LDO stage)

Stage 3 subtotal: ~0.64.** Earlier revisions of this page quoted **0.37 here; that figure counted the three regulators and left the seven bulk electrolytics out.

Stage 4: Protection and Rail Indicators (Board B)

PTC resettable fuses

Protection philosophy:

• PTC-only design — no backup fuses (traditional fuses are not available on JLCPCB assembly)

• Linear regulators act first: their current limiting is electronic and near-instant, while a PTC is thermal and takes seconds to trip. PTC1/2/3 are backstops for the case where the regulator's own protection is bypassed or defeated

• Four layers: USB-PD source → DC-DC → linear regulator → PTC

• Auto-reset: 30-60 s cooling, no manual fuse replacement

TVS diodes

Status indicator LEDs

All three indicator resistors are 1 kΩ. A "330 Ω for R8" figure appeared in older revisions of the circuit-diagram page; board_b_spec.py fits the same 1 kΩ 0805 line (C17513) at R7, R8 and R9. The +5 V indicator is therefore the dim one — ~2.2 mA against ~10 mA on the ±12 V rails.

Stage 4 subtotal: ~$0.82.

Stage 5: Output Connectors and Interface (Board B)

Eurorack power connectors (16-pin)

Connector type: standard 2×8 pin header (male, through-hole, 2.54 mm pitch).

Note: these are plain pin headers. For box/shrouded connectors (common in Eurorack), source the mating female box header separately — Tayda Electronics, Mouser/Digikey, or another distributor.

Eurorack 16-pin pinout (flipped for a bottom-facing PCB):

  GATE  [ 1]  [ 2]  GATE
  CV    [ 3]  [ 4]  CV
  +5V   [ 5]  [ 6]  +5V
  +12V  [ 7]  [ 8]  +12V
  GND   [ 9]  [10]  GND
  GND   [11]  [12]  GND
  GND   [13]  [14]  GND
  -12V  [15]  [16]  -12V   ← Red stripe side

Pins 9-14 are the GND moat, per board_b_spec.py's GND net (J10.9-J10.14, J11.9-J11.14) — six ground contacts per header, not the "n/c" pairs older revisions of this page showed.

Design note: the pinout is vertically flipped from the standard Eurorack orientation because the PCB mounts facing downward. Viewed from the module side (looking up at the PCB), the red stripe (-12 V) is at the bottom as expected.

Note: the GATE (pins 1-2) and CV (pins 3-4) rails are carried through to both headers but are not driven by this supply — they exist so a bus board sees a complete Eurorack header.

Individual power terminals

Purpose: direct wire or busboard connection. FASTON 250 terminals take thick-gauge wire for low-resistance, low-noise delivery. Requires matching FASTON receptacles. Combined GND return is ~2.5 A max — well inside the 7 A connector rating.

Interface, provisions, and test pads

P1 is placed as bare pads (in_bom = no, on_board = yes) per decision p1-form — the library carries no 2-pin test symbol, so the epic's "2-pin provision" resolves to a single 1×4 pad row with a probe ground return at zero BOM cost. ATT and PDOK are open-drain with no on-board pull-up on either board; any consumer wired to P1 must supply its own pull-up to its own logic rail.

**Stage 5 subtotal: ~1.28** (headers 0.16 + FASTON ~1.04 + J5 ~0.08).

Component Heights

Full height table and enclosure implications: Mechanical Design.

The tallest parts are the 470 µF electrolytics, then the FASTON terminals at 8.89 mm. Total board height is ~12 mm including the 1.6 mm PCB. The exact can height is stated once, in Mechanical Design — do not restate it here, so the two pages cannot drift apart again. Note that decision (d)'s C5/C7 swap moved those two positions from a D6.3 can to a D10 can, and decision neg-rail-cap-bank then added a new D10 can, C12, in parallel with C11 on the −13.5 V output. Board B now carries eight D10 electrolytics (C5, C7, C12, C14, C20, C21, C24, C25 are D10; C3, C9, C11 are D8; C4, C22, C23 are D6.3). C3/C11 were counted as D10 until issue #150: the fitted part there (C2983319, GVT1E477M0810CNVC) is a Φ8 × 10.5 mm can per its datasheet, and had simply been assigned the Φ10 land by mistake; C12 is a different, freshly-added position and was never subject to that mistake — it is a genuine Φ10 × 10.5 mm FOLLON can from the start.

Total Cost Summary

Notes:

• Prices are estimates from the JLCPCB part catalog and exclude PCB fabrication and assembly fees

• The PTC-only protection design removes the fuse line items entirely

JLCPCB Assembly Cost Structure

The component prices above are only part of the total PCBA cost. JLCPCB charges additional fees. The figures in this section describe the v4 single combined board — the design that was actually ordered four times. Board A and Board B have no layout or order files yet, so no split figures exist.

Fee Types

Basic vs Extended Parts

JLCPCB classifies components into two categories:

• Basic Parts: common resistors, MLCCs, some diodes — no extra fee

• Extended Parts: specialty ICs, electrolytic caps, LEDs, inductors, connectors — ¥470 per unique part number

The v4 single board used ~20 Extended parts, adding ~¥9,400 to the assembly cost. This is the number the split is designed to attack: Board A carries roughly 3-4 unique Extended parts, so a USB-PD-only debug iteration no longer re-pays for inductors, LDOs, electrolytics, and connectors that were never the failing part.

Cost Per Board (v4 single board, reference: January 2025)

Key insight: Extended fees are one-time setup costs, not per-board. Ordering more boards significantly reduces the per-unit cost.

Cost Optimization Tips

1. Order in batches of 5-10 to amortize setup fees

2. Hand-solder large components (electrolytic caps, connectors) to reduce Extended fees

3. Use Basic parts where possible (resistors, MLCCs are usually Basic)

4. Consolidate part numbers — fewer unique Extended parts = lower fees. Decision (d)'s C5/C7 swap onto the already-fitted 470 µF/35 V line is an instance of exactly this

Protection Circuit Operation

Normal operation (current below the PTC hold rating)

• PTC in its low-resistance state, minimal voltage drop

• Linear regulator in normal regulation

• Rail LED lit

PTC series resistance is a budget item, not free protection. The fitted SMD1210P150TF/16 has no retained resistance figure in this project's evidence base — the C20808 sibling's numbers belong to a different part and must not be substituted. The drop is a bench measurement against a ≤50 mV project budget at 1.2 A; see Board B → PTC1 voltage drop and acceptance testing.

Overload (current above the PTC hold rating)

1. PTC heats and its resistance rises

2. LED dims or goes out — the visible fault signal

3. PTC trips within seconds; rail current collapses

4. User action: reduce the load

5. Auto-recovery: 30-60 s to cool, then the rail returns

Short circuit (output shorted to GND)

1. Immediate: the linear regulator's own current limiting engages — electronic, essentially instant

2. Seconds: the PTC warms and trips under the limited current

3. Sustained: the regulator's thermal shutdown follows as its die heats

4. LED: off (fault indication)

5. Recovery: PTC and regulator both auto-reset after cooling

Key insight: the regulator limits current long before the PTC can react, which is what makes PTC-only protection adequate here. The PTC exists for the case where the regulator's own protection is bypassed — a shorted pass element, or a fault that does not route through the regulator at all.

Design Features

1. JLCPCB-sourceable

• Heavy use of Basic parts (resistors, MLCCs) — no per-part Extended fee

• Stock and price must be re-verified at order time for every line; several wave-6 picks were made against dated 2026-08-14 readings

• USB-PD IC: STUSB4500, USB-IF certified, 15 V support

2. Low-noise topology

• Two-stage: DC-DC for efficient conversion, linear regulator for the final low-noise output

• Target ripple: <1 mVp-p at the outputs (design intent, not yet measured)

3. Multi-layer protection

• Four layers: USB-PD source → DC-DC → linear regulator → PTC

• Auto-reset: no fuse replacement, 30-60 s recovery

• Visual feedback: per-rail status LEDs

• Board A additions: D5 clamps VBUS; D8 clamps Q1's gate-source against the unprogrammed-NVM 20 V case

4. Implementation

• SMD-first: compatible with automated PCBA assembly; the FASTON tabs and 2×8 headers are the THT exceptions

• Separated design: DC-DC and linear stages physically separated, and now the USB-PD front end is a separate board entirely