Linear Regulator PCB Layout and Thermal Design

Footprint, pad, copper-pour, thermal-via and capacitor-placement guidance for the U6/U7/U8 linear regulators, with the thermal budget recomputed from the recorded datasheet facts.

Layout input for the three final-stage linear regulators on Board B:

Terminal functions

Read this before drawing any pour. The tab is the single biggest layout trap on this stage, and it is not the same net on all three parts.

TO-263-2 (D2PAK) footprint - U6 and U7

         Top View (PCB Pad Layout)

    ┌──────────────────────────────┐
    │                              │
    │    Large Copper Pour         │  ← TAB = GND
    │    (6cm² recommended)        │     thermal + electrical
    │                              │
    │         Thermal Vias         │
    │         (6-10 vias)          │
    │                              │
    └──────────────────────────────┘

         PAD1 ■        PAD3 ■
        (INPUT)       (OUTPUT)

    Pin spacing: 2.54mm (0.1")
    Pin pad: 1.5mm x 2.0mm
    Tab pad: 10mm x 10mm (minimum)
            15mm x 15mm (recommended)

Recommended pad dimensions:

The project footprints already in the library are zudo-pd:TO-263-2_L10.0-W9.1-P5.08-LS15.2-TL (U6) and zudo-pd:TO-263-2_L10.0-W9.2-P5.08-LS15.3-TL-CW (U7).

TO-252-2L (DPAK) footprint - U8

The CJ7912 datasheet package outline is recorded in fact-cj7912-package-outline: body 6.5-6.7 mm x 6.0-6.2 mm, suggested pad layout tab 5.80 x 5.85 mm, lead span 4.57 mm. The datasheet marks its own pad layout "for reference purposes only". The project footprint is zudo-pd:TO-252-3_L6.5-W5.8-P4.58-BL.

Because the U8 tab carries -13.5V rather than ground, the tab pour is a floating island. Keep at least 2 mm of clearance between it and the ground pour, and more from any positive rail.

Layout recommendations

1. Component placement

   • Orient each IC with the tab facing the interior of the PCB, away from the edge.

   • Maximize copper area under and around the tab.

   • Keep the input and output capacitors on the same side as the regulator.

2. Copper pours

   • U6/U7: build a large ground pour (6 cm² minimum for U6, 5 cm² for U7) under and around the tab, tied into the main ground plane.

   • U8: build the -13.5V island under the tab, isolated from ground.

   • Bottom layer: additional copper reached through thermal vias.

   • Inner layers on a 4-layer board: further ground and power planes.

3. Thermal vias

   • 6-10 vias of 0.3 mm diameter under each tab, on roughly a 2 mm grid.

   • Connect to the matching net on the bottom layer - ground for U6/U7, the -13.5V island for U8.

   • Do not use thermal-relief spokes on these vias; a direct connection is the whole point.

4. Trace widths

   • U6 input (+13.5V) and output (+12V): 1 mm minimum for 1.2A.

   • U7 input (+7.5V) and output (+5V): 0.5 mm minimum for 0.5A; 1 mm on the output side keeps the drop negligible.

   • U8 input (-13.5V) and output (-12V): 1 mm minimum for 0.8A.

   • Ground: maximum available pour area.

   • High-current paths: 2 mm, or a pour.

5. Capacitor placement - the actual Board B pairs:

   Position	Input capacitors	Output capacitors
   U6 (+12V)	C14, C20 (470 µF 35V) on +13.5V OUT	C17 (100 nF), C21 (470 µF 35V) on Net-(U6-OUT)
   U7 (+5V)	C15 (470 nF), C22 (470 µF 10V) on +7.5V OUT	C18 (100 nF), C23 (470 µF 10V) on Net-(U7-OUT)
   U8 (-12V)	C16 (470 nF), C24 (470 µF 35V) on -13.5V OUT	C19 (100 nF), C25 (470 µF 35V) on Net-(U8-OUT)

   Placement distances: the ceramic within 5 mm of the input pad or output pad it serves, the bulk electrolytic within 10 mm. Note the asymmetry in the current spec - the U6 input pair is two electrolytics with no input ceramic, unlike the 470 nF that U7 and U8 each carry, so there is nothing to place close on that one position.

   fact-l7812cd2t-cap-input calls for 0.33 µF or larger directly across the input terminals with the shortest possible leads; fact-l7812cd2t-cap-output records that the L78 topology does not need an output capacitor for stability, so the output capacitors here are transient-response parts, not stability parts. For the CJ7912, fact-cj7912-esr-window-not-specified records that the Rev 2.0 datasheet states no output-capacitor ESR bounds, minimum capacitance, or stability window at all - so U8 output stability with this network is a bench question, not a datasheet question.

Thermal via pattern

    Thermal via pattern under a TO-263-2 tab:

    ┌─────────────────────────┐
    │  ●    ●    ●    ●    ●  │
    │                         │
    │  ●    ●    ●    ●    ●  │  ← 0.3mm vias
    │                         │     2mm spacing
    │  ●    ●    ●    ●    ●  │
    │                         │
    └─────────────────────────┘

    Minimum: 6 vias
    Recommended: 10 vias
    Aggressive: 15 vias

    Thermal via pattern under the TO-252-2L tab:

    ┌─────────────────────────┐
    │                         │
    │  ●    ●    ●    ●    ●  │
    │                         │  ← 0.3mm vias
    │  ●    ●    ●    ●    ●  │     2.5mm spacing
    │                         │
    └─────────────────────────┘

    Minimum: 6 vias
    Recommended: 8 vias
    Aggressive: 10 vias

Thermal budget

Dissipation is the series-pass product, headroom x rated current:

Applying the recorded junction-to-ambient figures at 25 °C ambient:

The U8 row is already recorded as a fact in its own right - fact-cj7912-tj-rise-full-load, verdict NEEDS BENCH.

Two caveats that decide how much weight these numbers carry:

• The conditions on fact-l7812cd2t-rthja and fact-l7805abd2t-rthja state that DS0422 gives no board, copper-area, or FR4 mounting condition for the 62.5 °C/W figure. It is a free-air-style bound, not a prediction for a board with a real copper pour.

• fact-cj7912-rthja is the only thermal-resistance figure the CJ7912 datasheet publishes - there is no junction-to-case value and no mounting condition either.

So the honest reading is: the datasheet numbers do not clear the junction limit, and the effective thermal resistance on the actual Board B copper has to be established by the layout thermal budget and then confirmed by bench measurement.

Design targets. To land at Tj = 110 °C with 25 °C ambient, the layout has to achieve:

If the copper pour cannot get there, the alternatives are to lower the headroom (retune the upstream DC-DC setpoint), de-rate the rail current, or add a heatsink. That is a design decision for the Board B layout wave, and it should be recorded, not assumed away.

+5V rail distribution

The +5V rail in a modular synthesizer feeds two quite different kinds of load.

Digital circuits (microcontrollers, logic ICs):

• Switching loads with transient current demand

• Decoupling: a 100 nF ceramic at every IC

• Distribution: star topology from the main filter capacitor

Analog circuits (op-amps, comparators):

• Steady loads, noise-sensitive

• Decoupling: 100 nF ceramic plus 10 µF electrolytic per section

• Isolation: an RC filter (10 Ω plus 100 µF) if needed

Low-noise operation

1. Additional output filtering - a 10 Ω resistor plus a 100 µF capacitor forms an extra pole near 160 Hz and knocks down high-frequency noise.

2. Separate analog and digital grounds - split the +5V distribution into analog and digital sections and join the grounds at a single star point, so digital switching noise does not couple into the analog side.

3. Shielding - route +5V traces away from high-frequency signals, use the ground plane as a shield, and keep sensitive analog circuitry away from digital sections.

Related

• DC-DC Converter Stage Design (LM2596S-ADJ) - the stage upstream

• Regulator Assembly, Soldering, and Inspection

• Power Rail Bench Test Procedure

• L7812CD2T, L7805ABD2T and CJ7912 are retired selections. Their owner evidence remains in the repository; use the renewed power stage for current regulator records.