Board Split Decision — Fix List + A/B Interface Contract

Locked decisions from the wave-2 decision pass (#90) - the front-end fix list for the existing KiCad project / Board A, the Board A to Board B interface contract with current-rating math, and the doc-structure assumption.

This page is the single source of truth for the three decision sets locked by the board-split decision task (epic #86, sub-issue #90). It consumes the three wave-1 analysis artifacts:

• v4 USB-PD Failure Diagnosis (#87) — ranked root causes + bench discrimination procedure

• v4 As-Built Order Verification & Footprint Geometry Audit (#88) — as-built and footprint verdicts

• Board B Architecture Review (#89) — DC-DC/LDO/protection review with 3 blockers

Decision set (a) — front-end fix list

A1. CCDB topology — LOCKED: restore CC1DB↔CC1 / CC2DB↔CC2, external Rd to DNP

Decision. Return to the ST reference wiring for a VBUS-only sink:

• CC1DB (U1 pin 1) joined to the CC1 line, and CC2DB (U1 pin 5) joined to the CC2 line, each through a 0 Ω link — implemented by repurposing the existing R19/R20 (0 Ω, LCSC C21189): their GND-side ends move from GND to the CC1/CC2 nets. The 0 Ω links double as fallback jumpers: removing them isolates the DB pins again for rework.

• R17/R18 (external 5.1 kΩ Rd, LCSC C23186) become DNP (footprints stay as rework insurance; excluded from BOM/CPL so JLCPCB never populates them).

Justification. Per the #87 diagnosis: DS12499 Rev 4 §7.3 Table 22 gives the STUSB4500 a non-disableable internal Rd of 5.1 kΩ ±10% whenever it is powered, so the v2→v4 topology (external 5.1 kΩ Rd + grounded DB pins) presents 2.55 kΩ effective the moment U1 boots — below the USB Type-C sink window (5.1 kΩ ±20%), landing the source-seen CC voltage inside or below the Ra/Rd undefined band (0.84 V at 3 A Rp). DS12499 §3.5 states dead-battery mode "is also used in systems that are powered through the VBUS only" — i.e. CCxDB↔CCx with no external Rd is ST's intended topology for exactly this board (also used by the SparkFun breakout and STEVAL-ISC005V1). The v2 "CC1DB chip-internal short" evidence that motivated the external-Rd redesign was re-examined in #87 and found inconclusive, while the redesign itself is a provable spec violation on every powered attach.

Fallback insurance. If bench test C2/C3 ever rehabilitates the bad-CCDB theory for a specific chip batch: remove R19/R20 (isolates the DB pins), fit R17/R18, and bodge the DB-side R19/R20 pads to GND — restoring the v4 topology without a board respin.

A2. VBUS ESD/TVS strategy — LOCKED: remove D4; SMAJ20A on VBUS; CC ESD provision DNP

Decision on D4 (USBLC6-2SC6, LCSC C7519): remove entirely (not relocate, not keep). Its two roles are re-covered separately:

1. VBUS clamp → SMAJ20A (SMA/DO-214AC, unidirectional): new part on VBUS_IN to GND, cathode on VBUS_IN. Primary pick: LCSC C571370 ("High Diode" brand — the same family and SMA footprint as the project's existing SMAJ15A / C571368 used for TVS1/TVS3, so the library symbol/footprint pattern is cloned, not invented). Alternate if C571370 is out of stock at order time: STMicroelectronics SMAJ20A-TR, LCSC C1973455. Stock was confirmed listed at LCSC on 2026-07-05; re-verify stock at order time.

   • Ratings: VRWM 20 V, VBR 22.2–24.5 V, clamping ≤32.4 V (10/1000 µs).

   • Why a 20 V standoff: the rail is 15 V by contract, so a 15 V-standoff part would sit at 0% margin (the exact mistake #89 flagged for TVS2/SD05 on the +5 V rail); 20 V standoff gives 33% margin at 15 V and stays non-conducting through the 20 V mis-contract edge case #89 guards against, while the ≤32.4 V clamp stays inside the LM2596S abs-max (40 V).

   • Residual (accepted): a hard surge clamp can momentarily exceed Q1/AO3401A's −30 V VDS rating; this is transient-only, far better than v4's 6 V zener on the 15 V rail, and Board A's layout phase may upgrade to an SMBJ20A if desired.

2. CC-line ESD → U1's integrated protection, plus a DNP provision. DS12499 rates the STUSB4500's CC pins for 22 V short-to-VBUS with integrated ESD structures — ST's own reference designs put nothing between the receptacle CC pins and the chip. The fitted Board A build therefore has no external CC ESD part (minimum parts between connector and chip, which is also what kills root-cause candidate 3 permanently — see A4). The Board A layout provisions two DNP footprints, one per CC line to GND: Nexperia PESD24VS1UB (SOD-523, unidirectional, VRWM 24 V, low capacitance), LCSC C85382 (stock confirmed listed 2026-07-05; re-verify at order time). VRWM 24 V is chosen deliberately above U1's 22 V CC fault rating so a fitted part never becomes the weakest link during a CC-short-to-VBUS fault; a 5 V-class USB ESD array on a PD CC line would repeat the D4 mistake. Fit them only for enclosed/production builds.

Why removal beats relocation. Keeping USBLC6-2 anywhere on this board is wrong by datasheet: its VBUS pin is a 6 V (min) zener, and its only remaining value — CC ESD — is already integrated in U1 at a higher fault rating (22 V vs the USBLC6's 5 V-class lines). Removal also converts the CC path from "two-pin nets joined inside a package" (candidate 3's silent-failure class) into plain copper.

A3. Pin-18 network — LOCKED: keep VBUS_IN → R14 (470 Ω) → pin 18 unchanged

DS12499 Rev 4 Table 1 specifies pin 18 (VBUS_VS_DISCH) as "From VBUS, receptacle side", and Table 22 (IDISUSB) specifies discharge "through external resistor connected to VBUS_VS_DISCH pin" at 50 mA max. With R14 = 470 Ω: 15 V / 470 Ω ≈ 32 mA, and even the 20 V edge case gives 20 V / 470 Ω ≈ 43 mA — both inside the 50 mA rating. #87 re-confirmed the network as-wired against the netlist, and #88 confirmed it reached the manufactured-package stage. No divider variant: pin 18 is simultaneously the receptacle-side discharge path and the VBUS presence sense; a divider would mis-scale the sense point and break the discharge function ST specifies through a single series resistor. Keep exactly as-is.

A4. Per-candidate disposition: fix-now vs bench-confirm-first

"Fix-now" = design-provable from datasheets, goes into the #93 KiCad edit regardless of which candidate actually killed v4. "Bench-confirm-first" = no design change until the stated gate from the #87 bench procedure resolves.

A5. #89's three Board-B blockers — explicit calls

Two #89 leads (not blockers) also get dispositions for the record:

• TVS2 (SD05, VRWM 5 V) at 0% standoff on the +5 V rail — defer to the Board B design phase; direction: replace with a ≥6 V-standoff part so the L7805's legal 4.8–5.2 V output never sits at/above the TVS standoff. Not in #93.

• C4/C22/C23 Value field says "16V" but C335982 is a 10 V part — fix-now in #93 as a Value-field-only correction (470uF 16V → 470uF 10V). Netlist-neutral, prevents a future reviewer trusting the wrong label. (10 V remains electrically safe on the 7.5 V/5 V nets per #89.)

A6. Exact #93 KiCad change list (the locked spec)

All edits in usb-pd-input.kicad_sch unless noted. No zudo-pd.kicad_pcb edits.

Explicitly NOT in #93: L7812 dropout rework (A5#1, bench-gated); TVS2 swap (Board B phase); PESD24VS1UB DNP footprints D6/D7 (Board A layout phase — adding never-fitted symbols to the legacy schematic is geometry risk with no payoff); any PCB edit.

Decision set (b) — Board A ↔ Board B interface contract

Connector — LOCKED: JST XH, 6 pins, one per board

• Board-side part (both boards): JST B6B-XH-A(LF)(SN), 6-pin top-entry shrouded through-hole header, 2.5 mm pitch — LCSC C144397 (genuine JST; ~42k stock listed at LCSC on 2026-07-05; re-verify at order time). Rated 3 A AC/DC per contact with AWG #22, 250 V.

• Cable: commodity pre-crimped 6-way XH↔XH lead, AWG 22, 80–150 mm; or build from JST XHP-6 housings + SXH-001T-P0.6 contacts (verify stock at order time — cable-side parts are not on the PCBA BOM).

• Why XH: polarized/shrouded housing (foolproof insertion), the de-facto synth-DIY standard, genuine-JST parts in JLCPCB's library, through-hole anchoring for a power connector, and cheap on both boards.

Pinout — LOCKED

Nothing synth-specific is on the connector: 15 V power, ground, and two generic open-drain status lines — Board A stays reusable as a plain "USB-PD 15 V sink module" in any other project (a consumer that ignores pins 3–4 just gets switched 15 V).

Current-rating math (3 A+ continuous)

Load basis — worst case is the PD contract cap of 3.0 A at 15 V, not the computed draw:

• Rated output budget: 12 V×1.2 A + 12 V×0.8 A + 5 V×0.5 A = 26.5 W.

• Estimated input at rated load: buck ≈85%, inverting ≈80% efficiency, LDO stage scales by Vout/Vin → per-rail input ≈ 19.1 W + 4.4 W + 13.5 W ≈ 37 W → 37 W / 15 V ≈ 2.5 A steady. The contract cap (3.0 A) is the design number.

GND uses the identical 2-contact math (symmetric return). 1.6× derated margin satisfies the project's 150%+ safety-margin convention. Cable drop is negligible: two paralleled AWG 22 conductors per leg at 100 mm ≈ 2.7 mΩ/leg → ≈16 mV round trip at 3 A.

Keying / foolproofing — LOCKED

• The XH shrouded housing is mechanically polarized — reversed insertion is blocked.

• Uniqueness rule: the 6-pin XH is the ONLY 6-position XH on either board, so the A↔B cable cannot land on a wrong header. (Board B's Eurorack outputs are 2×8 shrouded IDC; Faston tabs are physically incompatible.)

• Pin 1 is marked on silkscreen on both boards.

• The pinout is deliberately non-symmetric under pin reversal (+15V on 1–2, GND on 5–6) only behind the housing key; the key is the protection, the silkscreen is the audit.

Mechanical combination — LOCKED: side-by-side, cable-linked

• Side-by-side placement joined by the 6-way XH cable; stacking is rejected because: the USB-C receptacle must reach the enclosure wall on its own edge; Board A's J2 pogo pads must stay face-accessible for the NVM programming rig; Board B's three TO-263 regulators need top-side copper and airflow that a stacked board would blanket; and a stack fixes the relative orientation, hurting Board A reuse.

• Mounting: each board carries its own 4× M3 (3.2 mm) corner holes and mounts independently. Board A's hole pattern is chosen at layout time for Board A alone (no shared-pattern coupling to Board B). An optional shared 3D-printed tray can come later in 3dp-files/ — explicitly out of scope for this plan.

Decision set (c) — doc structure note

Assumption stated for reconciliation: the Board A / Board B pages go under overview/ as flat pages, matching the wave-3 issue defaults — overview/board-a-usb-pd-core.md, overview/board-b-synth-power.md, plus the housekeeping task's overview/two-board-plan.md. No dedicated boards/ section is created by this decision. If the housekeeping task (#94) instead creates a section, its PR description records that choice and the wave-4 confirm pass (#95) reconciles the paths (this page's links, the issue bodies, and the interface-table cross-references).

References

• v4 USB-PD Failure Diagnosis — candidates, DS12499 citations, bench procedure (gates referenced above)

• v4 As-Built Order Verification & Footprint Geometry Audit — footprint verdicts; v0.4.0 order-status caveat

• Board B Architecture Review — the three blockers dispositioned in A5

• PCBA v2 Debug Report — origin of the external-Rd topology reversed by A1

• NVM Programming Setup — read-back procedure behind the candidate-4 gate

• STUSB4500 pinout guide — ATT (pin 11) / POWER_OK2 (pin 20) roles used in the interface contract

• ST DS12499 Rev 4 (STUSB4500), ST USBLC6-2 datasheet, JST XH series datasheet, SMAJ series TVS datasheet — part-level claims above