Project Status and Plan
Historical reference
This page is retained from the previous design documentation. Parts, geometry, status and numerical claims may be superseded. Start with thecurrent architecture and verify exact components in thecatalog. See the archive guide for context.
Current progress and plan for the USB-PD powered modular synthesizer power supply — now in the 2-board split era following the v4 diagnosis (epic #86), with both boards now generated from spec-driven KiCad projects under boards/.
🎯 Project Goal
Low-noise power module supplying ±12V/+5V for modular synths from USB-C PD 15V input
Protection circuit safe for modular synth beginners
All parts available from JLCPCB (stable supply, low cost)
Low-noise design with <1mVp-p ripple
Easy to use with USB-C PD
🔄 Current Phase: Spec-Driven 2-Board Architecture
The single-board zudo-pd design (v1 → v4) never reached a working USB-PD negotiation, across four separate JLCPCB orders. Rather than order a v5 single-board respin, the project split into two boards:
Board A — a reusable USB-PD sink core (STUSB4500 + USB-C receptacle + load switch + NVM programming pads). Cheap to re-order in isolation while the front end is under debug, and reusable in other projects.
Board B — the synth power conversion stage (DC-DC converters + linear regulators + protection + output connectors). Carries the expensive/bulky parts, only re-ordered once the front end is proven stable.
Both boards now exist as real, generated KiCad projects under boards/board-a/ and boards/board-b/ — built by the schgen toolchain from Python spec modules (scripts/ / board_b_spec.py), not hand-drawn. A structured evidence review (epic #86's spec-architecture wave) locked a set of component-level fixes on top of the original board-split fix list — see Spec-Architecture Review for the findings and scripts/ for the machine-readable decision record.
See Two-Board Plan for the full why-split rationale, Board A: USB-PD Core and Board B: Synth Power for the per-board design docs, and Board Split Decision for the locked front-end fix list and the Board A ↔ Board B interface contract.
What's actually done vs. not started
Diagnosis, design docs, and both boards' generated schematics are done, including the wave-6 decision-locked part swaps (TVS2, PTC1, C5/C7, canonical 470µF LCSC numbers) and a new Q1 gate-source clamp (D8) on Board A. Not started: PCB layouts or JLCPCB order files (gerbers/BOM/CPL) for Board A or Board B. That is the next plan, gated on the user bench-confirming the v4 root cause on the dead v4 boards. The legacy root KiCad project (zudo-pd.kicad_pro etc.) stays in place, unregenerated, as the as-built v4 reference — see root CLAUDE.md.
Failure History (v1 → v4)
| Rev | Version | Result |
|---|---|---|
| v1 | 0.1.0 | PD failed — pin 18 (VBUS_VS_DISCH) left NC, pin 22 (VSYS) shorted to VREG_2V7 |
| v2 | 0.2.0 | CC1DB believed chip-internal short → external-Rd redesign |
| v3 | 0.3.0 | CC attach worked (5V, I2C alive), pin 18 tied to GND → PD failed |
| v4 | 0.4.0 | Pin 18 fixed, NVM programmed for 15V — still failed (see v4 USB-PD Failure Diagnosis for the ranked root-cause candidates) |
The v4 order artifacts (schematic + JLCPCB-ready manufacturing files) were confirmed to have actually reached a real order package — see v4 As-Built Order Verification & Footprint Geometry Audit.
✅ What's Done
Wave 1 (diagnosis): v4 USB-PD Failure Diagnosis (#87), v4 As-Built Audit (#88), Board B Architecture Review (#89)
Wave 2 (decision): Board Split Decision (#90) — locks the front-end fix list and the Board A ↔ Board B interface contract
Wave 3 (implement): Board A design doc, Board B design doc, confirmed schematic fixes applied to the legacy KiCad project
Spec-architecture epic (waves 1–8, epic #86): the
schgenspec-driven generator toolchain ported in;boards/andboard- a/ board- a. kicad_ sch boards/generated fromboard- b/ board- b. kicad_ sch board_a_spec.py/board_b_spec.py; a structured evidence review of both boards (Spec-Architecture Review); a wave-6 decision lock (scripts/) covering part swaps (TVS2 → SMAJ6.5A, PTC1 → SMD1210P150TF/16, C5/C7 → 470µF/35V FOLLON, canonical 470µF LCSC C335982), a new Q1 gate-source clamp (D8) on Board A, and the LM2596S-ADJ inverting-buck-boost topology wording (closes #46); this doc-base alignment pass (wave 8, #126)schgen/ decisions. json
📋 What's Next
Wave 9 and beyond: PCB layout for Board A / Board B, then the pre-order checklist (gerbers, BOM, CPL — explicitly not started; that is a separate future plan)
User action: bench-confirm the v4 root cause on the dead v4 boards using the bench discrimination procedure — this gates several of the locked fixes before the first Board A order
Versioning
See Versioning Scheme for the full X.Y.Z scheme, including how a 2-board JLCPCB order (Board A + Board B ordered together) is versioned going forward.
Hardware on Hand
NUCLEO-F072RB (STM32 Nucleo board, USB-to-I2C bridge for STUSB4500 NVM programming)
4P 2.54 mm pogo pin clip (mates with the J2 pogo pads) — see NVM Programming Setup
PCBA v1–v4 physical boards — retained for bodge reference and bench diagnosis (the v4 USB-PD Failure Diagnosis bench procedure runs on the dead v4 boards)