PCBA v2 Debug Report — STUSB4500 CC1DB Failure

Debug analysis of the second PCBA prototype (v2) for the USB-PD modular synthesizer power supply. The STUSB4500 was successfully programmed via NVM, but the chip's CC1DB pin is internally shorted to GND on every assembled board, preventing USB-C source detection and blocking PD negotiation entirely. This page documents the failure mode, diagnostic sequence, root cause analysis, and the v3 design fix.

Symptoms

After PCBA v2 was assembled by JLCPCB and the STUSB4500 NVM was successfully programmed:

Root Cause

The STUSB4500's CC1DB pin (pin 1) is internally shorted to GND.

CC1DB provides "dead battery mode" termination — a passive 5.1 kΩ Rd pulldown that the USB-C source detects in order to apply VBUS. Since CC1DB is internally shorted to 0 Ω instead of presenting 5.1 kΩ Rd, the source sees an invalid CC termination and refuses to enable VBUS.

The v2 schematic correctly ties CC1DB → CC1 net (the standard ST-recommended dead-battery wiring). With the chip's internal short, this wiring drags the entire CC1 net to GND.

Diagnostic Sequence That Isolated the Fault

Step 1: GUI Dashboard ruled out NVM and software

The STSW-STUSB002 GUI's Dashboard tab showed "No device attached" even with a USB-C cable plugged into a working PD charger. NVM-level settings cannot influence the chip's hardware CC detection — this proved the issue was at the physical CC pin level, not software.

Step 2: Multimeter measurements at D4 (USBLC6-2SC6)

D4 sits between the USB-C connector and the STUSB4500 on both CC lines. With board unpowered:

The asymmetry (CC1 shorted, CC2 fine) ruled out a generic short and pointed to a chip-side issue at pin 1 (CC1DB).

Step 3: Hot-air removal of U1 isolated the source

To definitively localize the short to the chip or the PCB:

1. Applied flux + hot air to U1 (STUSB4500), removed the chip

2. With chip off, measured pad 1 (CC1DB position on the empty footprint) to GND: OPEN circuit

3. PCB pads were visually clean — no solder bridges remained under the chip area

Conclusion: the chip was the source of the short. The PCB itself has no design or assembly defect on the CC1 net.

Step 4: Both PCBAs show identical fault

Two boards from the same JLCPCB order exhibited the exact same CC1DB short with the exact same chip placement orientation. This rules out:

• ❌ Random ESD damage (would affect chips randomly)

• ❌ Single-chip manufacturing defect

• ❌ Initial 20V overvoltage during testing (the second board was always programmed with a 5V-only charger first — confirmed by sequence of operations)

What We Ruled Out Through Investigation

Why v2 Design Is Vulnerable

The v2 schematic ties CC1DB ↔ CC1 and CC2DB ↔ CC2 — the standard ST-recommended dead-battery mode wiring used by:

• SparkFun Power Delivery Board (schematic)

• ST STEVAL-ISC005V1 evaluation board

• STUSB4500 datasheet "typical application" (Figure 10)

This design relies entirely on the chip's internal Rd for CC termination. There's no external fallback. If any chip ships with internally-damaged CC1DB or CC2DB pins, the entire board is bricked with no rework option short of chip replacement.

ST Datasheet Reference

Per the STUSB4500 datasheet (DS12499 Rev 5), pin description for CC1DB / CC2DB (page 4, Table 1):

Pin 1 CC1DB: "Dead battery enable on CC1 pin" — Typical connection: "To CC1 pin if used or ground"

Pin 5 CC2DB: "Dead battery enable on CC2 pin" — Typical connection: "To CC2 pin if used or ground"

And from §2.2.2 (page 5):

"CC1DB and CC2DB are used for dead battery mode. This mode is enabled by connecting CC1DB and CC2DB respectively to CC1 and CC2. Thanks to this connection, the pull-down terminations on the CC pins are present by default even if the device is not supplied."

⚠️ Warning: "CC1DB and CC2DB must be connected to ground when dead battery mode is not supported."

Both wiring options — "to CC1/CC2" (dead-battery) and "to ground" (no dead-battery) — are explicitly ST-supported. The v3 fix uses the second option.

v3 Design Fix

Topology change

v2 (vulnerable):                          v3 (robust):

USB-C CC1 ─┬─ D4 ─ STUSB4500 pin 2 (CC1)  USB-C CC1 ─┬─ D4 ─ STUSB4500 pin 2 (CC1)
           │                                          │
           └─────── STUSB4500 pin 1 (CC1DB)           R_CC1 (5.1 kΩ)   ← NEW
                                                      │
                                                     GND

                                          STUSB4500 pin 1 (CC1DB) ─── GND   ← CHANGED

(symmetric for CC2)                       (symmetric for CC2)

Schematic changes

Why 5.1 kΩ (and not 10 kΩ)?

5.1 kΩ is the USB-C spec Rd value (±20%, valid range 4.08–6.12 kΩ). Every USB-C sink uses this.

An earlier draft of this fix proposed 10 kΩ as a hedge in case a future chip batch ships with working internal Rd (so external + internal in parallel wouldn't drop too far below spec). That reasoning was rejected:

10 kΩ is out of spec in every scenario. 5.1 kΩ is in spec for our actual reality (broken chips, external Rd carries the load alone).

The "good chip" parallel-resistance failure mode is not solved by picking a compromise external value — the proper fix is to remove the external Rd entirely (board respin, or a populate/DNP jumper) once you know the chip's internal Rd is healthy. So for v3 we use the spec value and don't try to compromise across two failure scenarios.

Sensitivity on 3 A USB-C sources: sources advertising 3 A use Rp = 22 kΩ (tightest detection). The CC line voltage with Rp pull-up:

• 5.1 kΩ Rd → 5 V × 5.1 / (5.1 + 22) ≈ 0.94 V — comfortably below the ~1.7 V "sink connected" threshold

• 10 kΩ Rd → 5 V × 10 / (10 + 22) ≈ 1.56 V — borderline; some compliant sources will fail to detect

Why disconnect CC1DB / CC2DB from CC1 / CC2?

This is the critical change. If CC1DB stays on the CC1 net (v2 wiring), then a chip with internally-shorted CC1DB still drags the entire CC1 net to 0 Ω, and the external 5.1 kΩ is overpowered (a 0 Ω short wins against any finite resistor). The fault persists.

By routing CC1DB and CC2DB to GND directly:

• The broken pin's internal short is isolated to the GND net (harmless)

• The CC1 / CC2 nets see only the external R_CC1 / R_CC2 and the chip's main CC pins (pin 2, pin 4) for termination

What we give up: Dead-battery mode

In v3, the chip cannot present passive Rd before being powered. The chicken-and-egg is solved by the external R_CC1 / R_CC2 — these are always present and always provide valid Rd, so the source detects the sink, applies 5V VBUS, which powers the chip via VDD, which then takes over CC handling actively.

Dead-battery mode is only needed when the chip is being powered from a separate depleted battery and needs to advertise itself before that battery recovers. For VBUS-only powered designs like zudo-pd, dead-battery mode provides no benefit and creates the single-point-of-failure we hit.

Additional v3 Improvements (Recommended)

EPAD F.Paste aperture (footprint fix)

The current QFN-24 footprint defines pad 25 (the EPAD) with a single solid 2.8 × 2.8 mm F.Paste aperture. Standard QFN best practice is to window the EPAD paste into a grid of smaller apertures (e.g., 4×4 sub-squares of ~0.5 × 0.5 mm each, ~50-60% area coverage). This:

• Controls solder paste volume on the EPAD

• Prevents excess solder from squeezing out at the EPAD corners during reflow

• Reduces risk of solder bridging to corner pins (CC1DB is at one corner, RESET at the opposite corner)

• Is JLCPCB-recommended for thermal pad SMT assembly

EPAD GND vias (footprint fix)

The current EPAD has 16 GND vias in a 4×4 grid. Standard QFN recommendation is 4–9 vias for thermal/electrical GND connection. Excessive vias can wick solder away from the joint during reflow, contributing to solder migration and uneven joint quality.

Recommendation: Reduce to a 3×3 grid (9 vias) or 5 vias (4 corners + center). Use solder-mask plug on via-in-pad to prevent paste loss.

External Rd resistor placement

Place R_CC1 and R_CC2 physically close to the USB-C connector, before D4. This ensures the source's first measurement (at first cable plug) sees the external Rd directly, even if D4 or downstream traces have issues.

v3 Schematic Fix Checklist

• [x] Add R17 = R_CC1 (5.1 kΩ, 0603, 1%, C23186) from USB-C CC1 to GND

• [x] Add R18 = R_CC2 (5.1 kΩ, 0603, 1%, C23186) from USB-C CC2 to GND

• [x] Disconnect U1 pin 1 (CC1DB) from CC1 net; tie to GND via R19 (0 Ω, 0603, C21189) — uses a 0 Ω jumper instead of a direct GND tie so the chip-side net keeps the name CC1DB. That preserves a uniquely-named test point on the J3 pogo block (pin 1) for verifying chip-pin continuity, and lets us lift R19 for chip-isolation measurement during future debug

• [x] Disconnect U1 pin 5 (CC2DB) from CC2 net; tie to GND via R20 (0 Ω, 0603, C21189) — same rationale, J3 pogo pin 2

• [ ] Update QFN-24 footprint: window the EPAD F.Paste into a 4×4 grid of 0.5 mm² apertures

• [ ] Update QFN-24 footprint: reduce EPAD GND vias from 16 to 9 (or 5)

• [ ] Add via tenting / mask-plug on EPAD via-in-pad

• [ ] Run DRC and ERC

• [ ] Bench test on first v3 board: cold-plug a USB-C source, confirm VBUS appears (proves external Rd bootstrap works)

Reference Designs Compared

References

• STUSB4500 Datasheet DS12499 Rev 5 — pages 4, 5, 14, 23, 25, 26 referenced

• STUSB4500L Datasheet — variant with similar CC pin scheme

• STEVAL-ISC005V1 Schematic Pack — ST eval board reference

• STEVAL-ISC005V1 User Manual UM2547

• SparkFun Power Delivery Board Schematic (PDF)

• SparkFun Power Delivery Board product page

• DIY Smart Hotplate (Instructables) — working JLCPCB design with 10 kΩ external Rd on CC1

• GitHub: usb-c/STUSB4500 — official ST reference code

• USB Type-C 2.0 Specification — Rd termination requirements (§4.11.2)

• PCBA v1 Debug Report — v1 issues (different failure mode: pin 18 and pin 22 wiring)

• NVM Programming Setup — how to program the chip via STSW-STUSB002 GUI